參數(shù)資料
型號: SDA9400
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Scan Rate Converter using Embedded DRAM Technology Units
中文描述: 掃描頻率轉(zhuǎn)換器采用嵌入式DRAM技術(shù)股
文件頁數(shù): 6/94頁
文件大小: 1180K
代理商: SDA9400
SDA 9400
Micronas
6
Preliminary Data Sheet
TV mode detection by counting line numbers (PAL, NTSC, readable by I2C bus)
Embedded memory
- 5 Mbit embedded DRAM core for field memories
- 192 kbit embedded DRAM core for line memories
Flexible clock and synchronization concept
- Decoupling of the input and output clock system possible
Scan rate conversion
- Motion adaptive 100/120 Hz interlaced scan conversion
- Motion adaptive 50/60 Hz progressive scan conversion
- Simple static interlaced and progressive conversion modes
for 100/120 Hz interlaced or 50/60 Hz progressive scan conversion:
e.g. ABAB, AABB, AA*B*B, AAAA, BBBB, AB, AA*
- Simple progressive scan conversion with joint lines:
50 Hz -> 60, 70, 75 Hz progressive
60 Hz -> 70, 75 Hz progressive
- Large area and line flicker reduction
Flexible digital vertical expansion of the output signal (1.0, ... [1/32] ... , 2.0)
Flexible output sync controller
- Flexible positioning of the output signal
- Flexible programming of the output sync raster
- External synchronization by backend IC possible
(e.g. split screen for one TV channel with joint lines and one PC VGA channel)
Signal manipulations
- Insertion of coloured background
- Vertical and/or horizontal windowing with four different speed factors
- Flash generation (for supervising applications, motion flag readable by I2C bus)
- Still frame or field
- Support of split screen applications
- Multiple picture display - Tuner scan (4 and 16 times for 4:3, 12 times for 16:9 tubes)
- Support of multi picture display with PIP or front-end processor with integrated scaler
(e.g. 9 times display of PIP pictures, picture tracking, random pictures,
still-in-moving picture, moving-in-still picture)
I2C-bus control (400 kHz)
P-MQFP-64 package
3.3 V ± 5% supply voltage
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