參數(shù)資料
型號: SDA9400
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Scan Rate Converter using Embedded DRAM Technology Units
中文描述: 掃描頻率轉(zhuǎn)換器采用嵌入式DRAM技術股
文件頁數(shù): 13/94頁
文件大?。?/td> 1180K
代理商: SDA9400
SDA 9400
Micronas
13
Preliminary Data Sheet
Field detection and VIN delay
Input write parameter
In case of non-standard signals the field order is indeterminate (e.g. AAA... , BBB... , AAABAAAB...,
etc.). Therefore a special filtering algorithm is implemented, which can be switched on by the
parameter VCRMODE. It is recommended to set the parameter VCRMODE=1. In other case
(VCRMODE=0) an additional internal signal VTSEQ is generated. This signal goes high
(VTSEQ=1), if at least the last two fields were identical. Due to the fixed storage places of the fields
in the internal memory block, this information is necessary for the scan rate conversion processing
(see also
Output sync controller (OSC)
on page 40, it is recommended in case of VCRMODE=0 to
choose an adaptive operation mode).
The OPDEL parameter is used to adjust the outgoing V-Sync VOUT in relation to the incoming
delayed V-Sync VIN. In case of 50 Hz to 100 Hz interlaced scan rate conversion the OPDEL
parameter should be greater than half the number of lines of a field plus the internal processing
delay (8 lines).
Parameter
[Default value]
Subaddress
Description
VINDEL
[0]
FIEINV
1: Field A=1
0: Field A=0
[0]
VCRMODE
1: on
0: off
[1]
01h
Delay of the incoming V-Sync VIN (must be adjusted
depending on the delay of the HIN signal)
Inversion of the internal field polarity
00h
00h
In case of non standard interlaced signals (VCR, Play-
Stations) a filtering of the internal field signal has to be
done (should also be used for normal TV signals)
H1
H2
VIN
Ffd
Vd
CLK1
(VINDEL * 128 + 1) * Tclk1
Field 1(A)
Vd
Field 2(B)
Ffd
x
x
(VINDEL * 128 + 1) * Tclk1
VIN
f
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相關代理商/技術參數(shù)
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