參數(shù)資料
型號(hào): SDA9400
廠商: MICRONAS SEMICONDUCTOR HOLDING AG
英文描述: Scan Rate Converter using Embedded DRAM Technology Units
中文描述: 掃描頻率轉(zhuǎn)換器采用嵌入式DRAM技術(shù)股
文件頁(yè)數(shù): 38/94頁(yè)
文件大?。?/td> 1180K
代理商: SDA9400
SDA 9400
Micronas
38
Preliminary Data Sheet
Output signals
The SDA 9400 supports different clock concepts. In chapter 10 (see also
Application information
on page 90) a typical application of the circuit is shown. The front-end clock is connected to CLK1
input. The CLKOUT pin is connected to the back-end and the X1/CLK2 input is connected to a
crystal oscillator. The next figure explains the different clock switches, which may be used for the
separate modes (see also page 39, “Ingenious configurations of the HOUT and VOUT generator”).
Clock concept
Clock concept switching matrix
Signals
Pin number
Description
CLKOUT
26
Clock output
CLK11EN (19h)
CLK21EN (19h)
FREQR (1Bh)
CLKOUT
0
0
X
1
X
1
0
1
X
0
0
0
1
0
1
CLK1
not allowed
not allowed
CLK2_pll2
X1/CLK2
Clock
FREQR
Used in block
CLK1_pll1
CLK2_pll2
X1/CLK2
X
0
1
ISC, IFC, LDR, ED, MC, LM, I2C
OSC, HDR, ED, MC, LM, OFC
OSC, HDR, ED, MC, LM, OFC
c
CLK1
X1/CLK2
PLL1
PLL2
CLK21EN
CLK11EN
CLKOUT
1
0
0
1
CLK1_pll1
CLK2_pll2
0
1
FREQR
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