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參數(shù)資料
| 型號： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時鐘發(fā)生器的A/D轉(zhuǎn)換器) |
| 中文描述： | 在抗混疊濾波器和時鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時鐘發(fā)生器的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 9/54頁 |
| 文件大?。?/td> | 530K |
| 代理商： | SDA 9206 |
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SDA 9206
Semiconductor Group
9
1999-02-10
1.4
Pin Description
Pin No.
22, 36
21, 45
23, 55
32, 50
Symbol
V
SS
V
DD
V
SSQ
V
DDQ
Type
S
S
S
S
Description
Supply ground (
V
SS
) for digital parts
Supply voltage (
V
DD
) for digital parts
Supply ground for output stages and input stages
Supply voltage for output stages and
input stages (3.3 V / 5 V)
Analog positive supply voltage of ADC AINY (5 V)
Reference voltage high of ADC AINY (4.2 V)
Analog voltage input of ADC AINY input range
selectable via
I
2
C Bus (subaddress 11
H
, YAMP)
Reference voltage low of ADC AINY (2.2 V)
Analog ground of ADC AINY
Analog positive supply voltage of ADC AINU (5 V)
Reference voltage high of ADC AINU (4.2 V)
Analog voltage input of ADC AINU input range
selectable via
I
2
C Bus (subaddress 12
H
, UAMP)
Reference voltage low of ADC AINU (2.2 V)
Analog ground of ADC AINU
Analog positive supply voltage of ADC AINV (5 V)
Reference voltage high of ADC AINV (4.2 V)
Analog voltage input of ADC AINV input range
selectable via
I
2
C Bus (subaddress 12
H
, VAMP)
Reference voltage low of ADC AINV (2.2 V)
Analog ground of ADC AINV
Reset input signal: active low
Pin function defined by
I
2
C Bus:
Line frequent pulse output or
programmable digital control output
Reset output signal: active low; reset for other ICs
Blanking signal output, high level indicates
active video line
1
2
3
V
ADDY
V
REFHY
AINY
S
I/ana
4
5
6
7
8
V
REFLY
V
AGNDY
V
ADDU
V
REFHU
AINU
S
S
I/ana
9
10
11
12
13
V
REFLU
V
AGNDU
V
ADDV
V
REFHV
AINV
S
S
I/ana
14
15
16
17
V
REFLV
V
AGNDV
RESIN
H1I1
S
I/TTL/pu
Q/TTL
18
19
RESOUTN Q/TTL
BLN
Q/TTL
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