參數(shù)資料
型號(hào)： sda 9206
廠商： SIEMENS AG
英文描述： ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述： 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器）
文件頁(yè)數(shù)： 10/54頁(yè)
文件大?。?/td> 530K
代理商： SDA 9206
SDA 9206
Semiconductor Group
10
1999-02-10
1.4
Pin Description
(cont’d)
Pin No.
20
Symbol
H2I2
Type
Q/TTL
Description
Pin function defined by
I
2
C Bus:
Line frequent pulse output or
programmable digital control output
Data output Port A (
see Data Format
)
I
2
C-Bus data line
I
2
C-Bus clock line
I
2
C-Chip select
Data output port B (
see Data Format
)
Positive supply voltage of DTO (5 V)
Crystal connection
Crystal connection (clock input)
Ground of DTO
Vertical sync pulse output
Clock out: tristate / 6.75 / 13.5 / 27 MHz;
selectable via
I
2
C
Clock out: tristate / 6.75 / 13.5 / 27 MHz;
selectable via
I
2
C
Horizontal sync pulse output
Input signal for test mode selection
(0 V: no test mode selected)
Leave unconnected or connect to
V
SS
Input signal for test mode selection
(0 V: no test mode selected)
Leave unconnected or connect to
V
SS
Analog ground of analog PLL and DACs
Analog positive supply voltage of analog PLL
and DACs (5 V)
Analog ground of ADC SYNC
Reference voltage low of ADC SYNC (2.2 V)
SYNC input
Input range selectable via
I
2
C Bus
(subaddress 11
H
, SYNAMP)
24 ... 31
33
34
35
37 ... 44
46
47
48
49
51
52
PAQ7 ... 0 Q/TTL
SDA
SCL
ADR0
PBQ7... 0 Q/TTL
V
DDDTO
X2
X1
V
SSDTO
VS
CLK2
IQ
I
I/TTL/pd
S
Q/ana
I/ana
S
Q/TTL
Q/TTL
53
CLK1
Q/TTL
54
56
HS
TEST
Q/TTL
I/TTL/pd
57
EXSYN
I/TTL/pd
58
59
V
AGNDPA
V
ADDPA
60
61
62
V
AGNDC
V
REFLC
SYNC
I/ana
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sda 9254-2 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter(應(yīng)用于TV的2.6 M位動(dòng)態(tài)存儲(chǔ)器)
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