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| 型號(hào)： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器) |
| 中文描述： | 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 26/54頁 |
| 文件大?。?/td> | 530K |
| 代理商： | SDA 9206 |
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SDA 9206
Semiconductor Group
26
1999-02-10
2.3.4
To suppress bottom flutter in VCR mode, the frequency of the clock can be ’hold’ by
’freezing’ the increment of the HPLL. The vertical-frequency ’freezing-time’ starts a
number of lines (programmable by the
I
2
C Bus) before the vertical pulse and then lasts
for a number (programmable) of lines. The settings do not depend on
I
2
C-Bit TV. This
functionality is only available for the 1fh mode (2FH = 0).
Miscellaneous Circuit Sections
Figure 17
I
2
C-Bus Programming Area which Clock Frequency Value Generated by HPLL
can be Frozen
An active low reset signal for other chips is available at pin RESOUTN. It is activated
when the chip supply voltage
V
DD
is switched on or when voltage glitches occur on it.
RESOUTN also is activated by pin RESIN. The RESOUTN pulse signal is not cancelled
until the crystal oscillator resonates and in addition stretched by an internal circuit for
approximately 127 lines (8 ms).
n-2
n-1
n
1
2
3
4
5
Line Number
of Half Picture
(In this example the frequency value was frozen 13 lines before the VS pulse and for
a duration of 11 lines.)
0
1
10
11
12
13
14
15
15
14
13
12
3
2
1
0
Range over which
Frequency Value
is Frozen
Start 0...15 Lines before VS
Start
Stop
0...15 Lines Duration
n = Number of Lines
in preceding Half Picture
UED10466
VS
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