參數(shù)資料
型號： sda 9206
廠商： SIEMENS AG
英文描述： ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述： 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器）
文件頁數(shù)： 29/54頁
文件大?。?/td> 530K
代理商： SDA 9206
SDA 9206
Semiconductor Group
29
1999-02-10
2.4.4
Subaddress 00
H
Bit
D7
D6
Detailed Description
Name
0
UV3FIL
Function
Reserved
Filter stage 3 for UV data (FORMAT = 0X)
0:
OFF
1:
ON
Note:
For FORMAT = 1X filter stage 3 for UV data is “on”
(UV3FIL = don′t care)
FORMAT Selection of output data interface:
00:
Output data format according CCIR 656 (8 wires at Port A)
01:
Parallel output data format (2 x 8 wires)
10:
Quasiparallel 12 wire interface
11:
Quasiparallel 12 wire interface
UVCODE Coding of UV data:
0:
Straight binary code
1:
Two’s complement code
YCODE
Coding of Y data:
0:
Straight binary code
1:
Two’s complement code
OENB
Output enable port B:
0:
Tristate
1:
Port enabled
OENA
Output enable port A:
0:
Tristate
1:
Port enabled
D5...D4
D3
D2
D1
D0
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