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參數(shù)資料
| 型號(hào)： | sda 9206 |
| 廠商： | SIEMENS AG |
| 英文描述： | ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器) |
| 中文描述： | 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器） |
| 文件頁數(shù)： | 18/54頁 |
| 文件大?。?/td> | 530K |
| 代理商： | SDA 9206 |
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SDA 9206
Semiconductor Group
18
1999-02-10
The frequency response of the decimator filter stage 3 of the UV channels for an input
sampling rate of 6.75 MHz and an output sampling rate of 3.375 MHz is shown in
figure 13
. The decimator stage 3 is active for 4:1:1 mode and can also be activated for
4:2:2 mode by
I
2
C Bus (control bit UV3FIL).
Figure 13
Frequency Response of the Chroma Decimator Stage 3
The Input Sampling Frequency
f
S
is 6.75 MHz
2.2
Three output data formats can be selected via
I
2
C Bus (control Bits FORMAT). One
format corresponds to CCIR 656 (8-Bit bus at a data rate of 27 MHz), an other format
makes available Y and UV data separately on 2 parallel 8-Bit buses for Y and UV at a
data rate of 13.5 MHz each. The third format is a 12-Bit bus with 8 connections for Y and
4 connections for multiplexed UV data.
Data Output Formatter
-20
-30
-40
0.2
0
0.1
-50
-10
dB
10
0
0.5
0.3
0.4
UED10461
A
f / f
S
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