參數(shù)資料
型號(hào)： sda 9206
廠商： SIEMENS AG
英文描述： ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的A/D轉(zhuǎn)換器)
中文描述： 在抗混疊濾波器和時(shí)鐘產(chǎn)生單元內(nèi)置模數(shù)轉(zhuǎn)換器（帶有片內(nèi)去混疊和時(shí)鐘發(fā)生器的的A / D轉(zhuǎn)換器）
文件頁數(shù)： 48/54頁
文件大小： 530K
代理商： SDA 9206
SDA 9206
Semiconductor Group
48
1999-02-10
3.2
Characteristics (Assuming Recommended Operating Conditions)
(cont’d)
Parameter
Symbol
Limit Values
nom.
Unit
Remark
min.
max.
25
Output data delay time,
referenced to CLK1
(not valid for ESOUTN)
t
QD
35
25
ns
ns
ns
DATDEL = 000
C
L
= 15 pF
5 V output stage
supply voltage,
DATSLOP = 0
DATDEL = 000
C
L
= 25 pF
5 V output stage
supply voltage,
DATSLOP = 0
DATDEL = 000
C
L
= 25 pF
3.3 V output stage
supply voltage,
FORMAT = 00
DATSLOP = 1
Output data hold time,
referenced to CLK1
(not valid for
RESOUTN)
Pin RESOUTN
Data delay/
data hold time
Clock TTL Outputs CLK1, CLK2
L-output voltage
H-output voltage
Load capacitance
Transition times
t
QH
6
ns
-
-
-
Asynchronous output
signal
V
QL
V
QH
C
L
t
R
,
t
F
0
2.4 V
0.4
V
DD
30
5
V
1
pF
ns
I
= 1 mA
I
= - 0.5 mA
5 V output stage
supply voltage,
CLKSLOP = 00
3.3 V output stage
supply voltage,
CLKSLOP = 10
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