
Philips Semiconductors
Preliminary specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
1998 Sep 21
4
SClk
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CEN
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NOTE:
1. Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf). These edges may move as fast as 1 to 3 ns fall
or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See
previous note on Sclk noise under pin assignments.
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Write Read not control: When high indicates that the host CPU will write to a 28L194 register or transmit FIFO.
When low, indicates a read cycle. 0 = Read; 1 = Write
O
Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete.
interrupt(s).
Open drain requires a pull-up device.
I
Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt
Receive Data: Serial inputs to the 4 UARTs
I/O
Input/Output 0: Multi-use input or output pin for the UART.
I/O
Input/Output 1: Multi-use input or output pin for the UART.
Global general purpose inputs, available to any/all channels.
O
Global general purpose outputs, available from any channel.
I
Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and
Crystal 1 or Communication Clock: This pin may be connected to one side of a 2-8 MHz crystal. It may
alternatively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz
O
Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin
must be left unconnected.
16 pins total 8 pins for Vss, 8 pins for Vcc
twice the frequency of highest X1, Counter/Timer, TxC (1x) or RxC (1x) input frequency.
Chip select: Active low. When asserted, allows I/O access to QUART registers by host CPU. W_RN signal
8-bit bi-directional data bus. Carries command and status information between 28L194 and the host CPU.
Used to convey parallel data for serial I/O between the host CPU and the 28L194
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Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater than
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DACKN
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IACKN
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I/O0(a-d)
I/O1(a-d)
Gout(1:0)
RESETN
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W_RN
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IRQN
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X1/CCLK
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Power Supplies
X2
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V
Voltage from V
to V
V
SS
Voltage from any pin to V
SS
Derating factor above 25
C (LQFP package)
NOTES:
the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is
not implied.
2. For operating at elevated temperatures, the device must be derated based on +150
°
C maximum junction temperature.
3. Parameters are valid over specified temperature range. See Ordering Information table for applicable temperature range and operating
supply range.
4. This product includes circuitry specifically designed for the protewction of its internal devices from damaging effects of excessive static
charge.
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-0.5 to +7.0
-0.5 to V
CC
+ 0.5
16
V
V
mW/
C
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