參數(shù)資料
型號: SC28L194
廠商: NXP Semiconductors N.V.
英文描述: Quad UART for 3.3V and 5V supply voltage(在3.3V和5V電源電壓中應(yīng)用的四 UART)
中文描述: 四UART的3.3V和5V電源電壓(在3.3和5V的電源電壓中應(yīng)用的四UART)的
文件頁數(shù): 39/52頁
文件大?。?/td> 294K
代理商: SC28L194
Philips Semiconductors
Preliminary specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
1998 Sep 21
39
AC ELECTRICAL SPECIFICATIONS FOR COMMERCIAL AND INDUSTRIAL (3.3V)
(continued)
V
CC
= 3.3V
±
10%, –40 to +85
°
C
SYMBOL
FIG #
FIG. #
PARAMETER
LIMITS
TYP.
UNIT
MIN.
MAX.
Sclk Timing
t
sclkl
t
sclkh
F
sclk
t/
RFsck
X1/X2 Communication Crystal Clock
Fx1
5
Min low time at V
IL
(0.8V)
Min high time at V
IH
(2.0V)
Sclk frequency
15
10
ns
15
10
ns
0.1
20
MHz
Sclk rise and fall time (0.8 to 2.0 Volts)
5
ns
X1 clock frequency
1
3.6864
4.0
MHz
X1 L / H
X1 Low / High time
80
135
ns
T/RFx1
X1 Rise and Fall time
10
ns
Counter/Timer Baud Rate Clock (External Clock Input)
FC/T
4
Clock frequency
0
8
MHz
TC/TLH
C/T high and low time
20
15
ns
TC/TO
Delay C/T clock external to output pin
48
110
ns
DACKN Timing
DAK
DLY
DAK
DLYA
DAK
DLYS
I/O Port External Clock
DACK low from Sclk C4 rising edge
18
30
ns
DACK high from CEN high (Async)
18
30
ns
DACK high from C4 end rising edge (Sync)
20
30
ns
T
GPIRTX
GPI to Rx/Tx clock out
50
80
ns
RxD setup to I/OP rising edge 1X mode
20
2
ns
I/OP falling edge to TxD out 1X mode
32
70
ns
G
OUT
Timing
GPO
TDD
NOTES:
1. Timing is illustrated and referenced with respect to W-RN and CEN inputs. Internal read and write activities are controlled by the Sclk as it
generates the several “C” timing as shown in the timing diagrams.
2. The minimum time before the rising edge of the next C2 time to stop the next bus cycle. CEN must return high after midpoint of C4 time and
before the C2 time of the next cycle.
3. Delay is from cEN high in Async mode to IRQN inactive, from end of C4 to IRQN inactive in Sync mode.
4. The minimum frequency values are not tested, but are guaranteed by design.
5. 1MHz specification is for crystal operation.
GPO valid after write to GPOR
100
ns
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