
Philips Semiconductors
Preliminary specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
1998 Sep 21
24
Table 12.
Bit 6
I/O Port change
of state
Time-out
áááááááááááááááááááááááááááá
áááááááááááááááááááááááááááá
á
ááááááááááááááááááááááááááááá
The programming of this register selects which bits in the ISR cause
an interrupt output. If a bit in the ISR is a ’1’ and the corresponding
bit in the IMR is a ’1’, the interrupt source is presented to the internal
interrupt arbitration circuits, eventually resulting in the IRQN output
being asserted (low). If the corresponding bit in the IMR is a zero,
the state of the bit in the ISR has no affect on the IRQN output.
IMR[7] -
Controls if a change of state in the inputs equipped with
input change detectors will cause an interrupt.
Bit 7
Bit 5
Bit 4
Table 15.
Bit 3
BCRBRK - Bidding Control Register -
Break Change
Bits 7:3
Reserved
MSB of break change interrupt bid
for a break change interrupt.
Bit 2
Bit 1
Bit 0
á
á
Receiver Watch-dog
áááá
á
ááá
á
á
á
ááá
Break State
á
interrupt
á
RxRDY
interrupt
á
TxRDY
IMR[6] -
Controls the generation of an interrupt by the watch-dog
timer event. If set, a count of 64 idle bit times in the receiver will
begin interrupt arbitration.
IMR[5] -
Enables the generation of an interrupt in response to
changes in the Address Recognition circuitry of the Special Mode
(multi-drop or wake-up mode).
IMR[4] -
Enables the generation of an interrupt in response to
recognition of an in-band flow control character.
IMR[3] -
Reserved
IMR[2] -
Enables the generation of an interrupt when a Break
condition has been detected by the channel receiver.
IMR[1] -
Enables the generation of an interrupt when servicing for
the RxFIFO is desired.
IMR[0] -
Enables the generation of an interrupt when servicing for
the TxFIFO is desired.
Table 13.
Bit[10]
Break
Status
RxFIFO Receiver FIFO
Bit[9]
Framing
Status
ááááááááááááááá
ááááááááááááááá
á
ááááááááááááááá
status of each byte received is stored with that byte and is moved
along with the byte as the characters are read from the FIFO. The
upper three bits are presented in the STATUS register and they
change in the status register each time a data byte is read from the
FIFO. Therefor the status register should be read BEFORE the byte
is read from the RxFIFO if one wishes to ascertain the quality of the
byte
Bit[8]
Parity
Status
Bits [7:0]
8 data bits
áá
á
áá
á
áá
á
áááááá
data
á
The forgoing applies to the “character error” mode of status
reporting. See MR1[5] and “RxFIFO Status” descriptions for “block
error” status reporting. Briefly “Block Error” gives the accumulated
error of all bytes received in the RxFIFO since the last “Reset Error”
command was issued. (CR = x’04)
Table 14.
TxFIFO - Transmitter FIFO
Bits 7:0
8 data bits. MSBs set to 0 for 7, 6, 5 bit data
ááááááááááááááááá
ááááááááááááááááá
The FIFO for the transmitter is 8 bits wide by 16 bytes deep. For
character lengths less than 8 bits the upper bits will be ignored by
the transmitter state machine and thus are effectively discarded.
ááááááá
áááááááááááááááá
ááááááááááá
Bits 2:0
áááááááááááááááá
Table 16.
BCRCOS - Bidding Control Register -
for a Change of State, COS, interrupt.
áááááááááááááááá
áááááááááááááááá
áááááááááááááááá
áááááááááááááááá
Table 17.
BCRx - Bidding Control Register -
áááááááááááááááá
áááááááááááááááá
This register provides the 3 MSBs of the Interrupt Arbitration number
for an Xon/Xoff interrupt.
áááááááááááááááá
Table 18.
BCRA - Bidding Control Register -
Address
Bits 7:3
Reserved
ááááááá
áááááááááááááááá
áááááááááááááááá
This register provides the 3 MSBs of the Interrupt Arbitration number
for an address recognition event interrupt.
ááááááááááá
Bits 2:0
Table 19.
XonCR - Xon Character Register
Bits 7:0
ááááááááááááááááá
ááááááááááááááááá
An 8 bit character register that contains the compare value for an
Xon character.
ááááááááááááááááá
ááááááááááááááááá
ááááááááááááááááá
An 8 bit character register that contains the compare value for an
Xoff character.
ááááááááááááááááá
Table 21.
ARCR - Address Recognition Character
Register
8 Bits of the Multi-Drop Address Character Recognition
ááááááááááááááááá
ááááááááááááááááá
wake-up address character.
ááááááááááááááááá