參數(shù)資料
型號: SC28L194
廠商: NXP Semiconductors N.V.
英文描述: Quad UART for 3.3V and 5V supply voltage(在3.3V和5V電源電壓中應用的四 UART)
中文描述: 四UART的3.3V和5V電源電壓(在3.3和5V的電源電壓中應用的四UART)的
文件頁數(shù): 25/52頁
文件大?。?/td> 294K
代理商: SC28L194
Philips Semiconductors
Preliminary specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
1998 Sep 21
25
Table 22.
Status
00 - none
01 - Xoff received
10 - Xon received
XISR - Xon-Xoff Interrupt Status Register
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transmission status
00 - none
01 - Xon transmitted
10 - Xoff transmitted
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10 - Xoff in pending
XISR[7:6] -
Received X Character Status. This field can be read to
determine if the receiver has encountered an Xon or Xoff character
in the incoming data stream. These bits are maintained until a read
of the XISR. The field is updated by X character reception
regardless of the state of MR0(7, 3:2) or IMR(4). The field can
therefore be used as a character detector for the bit patterns stored
in the Xon and Xoff Character Registers.
XISR[5:4] -
Automatic transmission Status. This field indicates the
last flow control character sent in the Auto Receiver flow control
mode. If Auto Receiver mode has not been enabled, this field will
always read b’00. It will likewise reset to b’00 if MR0(3) is reset. If
the Auto Receiver mode is exited while this field reads b’10, it is the
user’s responsibility to transmit an Xon, when appropriate.
XISR[3:2] -
TxD flow Status. This field tracks the transmitter’s flow
status as follows:
00 - normal. The flow control is under host control.
01 - TxD halt pending. After the current character finishes the
transmitter will stop. The status will then change to b’00.
10 - re-enabled. The transmitter had been halted and restarted. It
is sending data characters. After a read of the XISR, it will return
to “normal” status.
11 - disabled. The transmitter is flow controlled.
XISR[1:0] -
TxD character Status. This field allows determination of
the type of character being transmitted. If XISR(1:0) is b’01, the
channel is waiting for a data character to transfer from the TxFIFO.
This condition will only occur for a bit time after an Xon or Xoff
character transmission unless the TxFIFO is empty.
Table 23.
WDTRCR - Watch-dog Run Control
Register
Bit 3
Bit 2
WDT d
WDT c
0 off
0 off
receivers on the Quad UART
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Bits 7:4
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Bit 1
WDT b
0 off
Bit 0
WDT a
0 off
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Table 24.
BRGTRU
-
BRG Timer Reload
Registers, Upper (Timers A & B)
8 MSB of the BRG Timer divisor.
This is the upper byte of the 16 bit value used by the BRG timer in
generating a baud rate clock
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Table 25.
BRGTRL
-
BRG Timer Reload
Registers, Lower (Timers A & B)
Bits 7:0
8 LSB of the BRG Timer divisor.
This is the lower byte of the 16 bit value used by the BRG timer in
generating a baud rate clock.
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