Philips Semiconductors
Preliminary specification
SC28L194
Quad UART for 3.3V and 5V supply voltage
1998 Sep 21
20
Table 6.
Both registers consist of single 5 bit field that selects the clock source for the receiver and transmitter, respectively. The unused bits in this
register read b’000. The baud rates shown in the table below are based on the x1 crystal frequency of 3.6864MHz. The baud rates shown below
RxCSR and TxCSR - Receiver and Transmitter Clock Select Registers
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Table 7.
Bits 4:0
CCLK = 3.6864 MHz
00000
BRG - 50
00001
BRG - 75
00101
BRG - 450
00110
BRG - 600
01010
BRG - 2400
01011
BRG - 3600
01111
BRG - 14.4K
Data Clock Mux
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11010
11111
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10000
10101
10110
Reserved
Reserved
Clock Select Code
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CCLK = 3.6864 MHz
BRG - 19.2K
BRG - 28.8K
BRG - 230.4K
Gin0
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11011
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10001
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I/O2 rcvr, I/O3 xmit -16x
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Table 8.
CR is used to write commands to the Quad UART.
Bits 7:3
Channel Command codes see
“Command Register Table”
CR - Command Register
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CR[2] - Lock TxD and RxFIFO enables
If set, the transmitter and receiver enable bits, CR[1:0] are not
significant. The enabled/disabled state of a receiver or transmitter
can be changed only if this bit is at zero during the time of the write
to the command register.
WRITES TO THE UPPER BITS OF THE
CR WOULD USUALLY HAVE CR[2] AT 1
to maintain the condition
of the receiver and transmitter. The bit provides a mechanism for
writing commands to a channel, via CR[7:3], without the necessity of
keeping track of or reading the current enable status of the receiver
and transmitter.
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Bit 2
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received will be lost. The command has no effect on the receiver
status bits or any other control registers. If the special wake-up
mode is programmed, the receiver operates even if it is disabled
(see Wake-up Mode).
Bit 1
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Bit 0
0 = Change Tx & Rx enable conditions
1 = Hold present condition of Tx & Rx Enables
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CR[1] - Enable Transmitter
A one written to this bit enables operation of the transmitter. The
TxRDY status bit will be asserted. When disabled by writing a zero
to this bit, the command terminates transmitter operation and resets
the TxRDY and TxEMT status bits. However, if a character is being
transmitted or if characters are loaded in the TxFIFO when the
transmitter is disabled, the transmission of the all character(s) is
completed before assuming the inactive state.
CR[0] - Enable Receiver
A one written to this bit enables operation of the receiver. If not in
the special Wake-up mode, this also forces the receiver into the
search for start bit state. If a zero is written, this command
terminates operation of the receiver immediately - a character being
CR[7:3] - Miscellaneous Commands
(See Table below)
The encoded value of this field can be used to specify a single
command as follows:
00000
No command.
00001
Reserved.
00010
Reset receiver. Resets the receiver as if a hardware reset
had been applied. The receiver is disabled and the FIFO
pointer is reset to the first location effectively discarding all
unread characters in the FIFO.
00011
Reset transmitter. Resets the transmitter as if a hardware
reset had been applied.
00100
Reset error status. Clears the received break, parity error,
framing error, and overrun error bits in the status register
(SR[7:4]). Used in character mode to clear overrun error
status (although RB, PE and FE bits will also be cleared),
and in block mode to clear all error status after a block of
data has been received.
00101
Reset break change interrupt. Causes the break detect
change bit in the interrupt status register (ISR[2]) to be
cleared to zero.