參數(shù)資料
型號: SC16C752BIB48
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit-s (max.), with 64-byte FIFOs
封裝: SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁數(shù): 35/47頁
文件大?。?/td> 945K
代理商: SC16C752BIB48
SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
35 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
[1]
RCLK is an internal signal derived from Divisor Latch LSB (DLL) and Divisor Latch MSB (DLM) divisor latches.
[2]
Applies to external clock; crystal oscillator max 24 MHz.
[3]
Reset pulse must happen when CSA, CSB, IOR, IOW are inactive.
11.1 Timing diagrams
t
su2
t
su3
data set-up time
set-up time from IOW or IOR assertion to
XTAL1 clock LOW-to-HIGH transition
IOR strobe width
IOW strobe width
16
20
-
-
16
20
-
-
ns
ns
t
w1
t
w2
77
30
-
-
30
30
-
-
ns
ns
Table 26.
T
amb
=
40
°
C to +85
°
C; V
CC
= 2.5 V, 3.3 V
±
10 % or 5 V
±
10 %, unless specified otherwise.
Symbol
Parameter
Dynamic characteristics
…continued
Conditions
V
CC
= 2.5 V
Min
V
CC
= 3.3 V or 5 V Unit
Min
Max
Max
Fig 14. General read timing
data
active
active
valid
address
002aaa235
A0 to A2
CSA, CSB
IOR
D0 to D7
t
d3
t
d4
t
d1
t
w1
t
d2
t
h4
t
su1
t
h1
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