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| 型號： | SC16C752BIB48 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 收發(fā)器 |
| 英文描述： | 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit-s (max.), with 64-byte FIFOs |
| 封裝： | SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html& |
| 文件頁數(shù)： | 30/47頁 |
| 文件大?。?/td> | 945K |
| 代理商： | SC16C752BIB48 |
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SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
30 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.13 Trigger Level Register (TLR)
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for
DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a
granularity of 4.
Table 21
shows trigger level register bit settings.
Table 21.
Bit
7:4
3:0
Remark:
TLR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. If
TLR[3:0] or TLR[7:4] are logic 0, the selectable trigger levels via the FIFO Control
Register (FCR) are used for the transmit and receive FIFO trigger levels. Trigger levels
from 4 bytes to 60 bytes are available with a granularity of four. The TLR should be
programmed for
N
4
, where N is the desired trigger level.
When the trigger level setting in TLR is zero, the SC16C752B uses the trigger level setting
defined in FCR. If TLR has non-zero trigger level value, the trigger level defined in FCR is
discarded. This applies to both transmit FIFO and receive FIFO trigger level setting.
When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,
i.e., ‘00’.
7.14 FIFO ready register
The FIFO ready register provides real-time status of the transmit and receive FIFOs of
both channels.
Table 22.
Bit
7:6
5
4
3:2
1
0
The FIFO Rdy register is a read-only register that can be accessed when any of the two
UARTs is selected CSA or CSB = logic 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and
loopback is disabled. The address is 111.
Trigger Level Register bits description
Symbol
Description
TLR[7:4]
receive FIFO trigger levels (4 to 60), number of characters available
TLR[3:0]
transmit FIFO trigger levels (4 to 60), number of spaces available
FIFO Ready Register bits description
Symbol
Description
FIFO Rdy[7:6]
unused; always 0
FIFO Rdy[5]
receive FIFO B status. Related to DMA.
FIFO Rdy[4]
receive FIFO A status. Related to DMA.
FIFO Rdy[3:2]
unused; always 0
FIFO Rdy[1]
transmit FIFO B status. Related to DMA.
FIFO Rdy[0]
transmit FIFO A status. Related to DMA.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C752BIB48,128 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C752BIB48,151 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C752BIB48,157 | 功能描述:UART 接口集成電路 2CH. UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C752BIB48151 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| SC16C752BIB48-F | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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