參數(shù)資料
型號: SC16C752BIB48
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 2.2 V and 2.5 V dual UART, 5 Mbit-s (max.), with 64-byte FIFOs
封裝: SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C752BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁數(shù): 22/47頁
文件大小: 945K
代理商: SC16C752BIB48
SC16C752B
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NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
22 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling.
Table 11
shows FIFO control register bit settings.
Table 11.
Bit
7:6
FIFO Control Register bits description
Symbol
Description
FCR[7] (MSB),
FCR[6] (LSB)
00 - 8 characters
01 - 16 characters
10 - 56 characters
11 - 60 characters
FCR[5] (MSB),
FCR[4] (LSB)
00 - 8 spaces
01 - 16 spaces
10 - 32 spaces
11 - 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’
logic 1 = set DMA mode ‘1’
FCR[2]
Reset transmit FIFO.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = Clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
FCR[1]
Reset receive FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO.
RX trigger. Sets the trigger level for the receive FIFO.
5:4
TX trigger. Sets the trigger level for the transmit FIFO.
3
2
1
0
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