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| 型號(hào)： | SAH-XC2712X-8F66R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PDSO38 |
| 封裝： | 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38 |
| 文件頁數(shù)： | 83/103頁 |
| 文件大?。?/td> | 2957K |
| 代理商： | SAH-XC2712X-8F66R |
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XC2712X
XC2000 Family / Compact Line
Electrical Parameters
PRELIMINARY
Data Sheet
76
V1.0, 2010-12
This is especially important for bus cycles using waitstates and for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler K2 to generate the system clock signal
f
SYS. The number of VCO cycles
is K2
× T, where T is the number of consecutive f
SYS cycles (TCS).
The maximum accumulated jitter (long-term jitter) DTmax is defined by:
DTmax [ns] = ±(220 / (K2 × fSYS) + 4.3)
This maximum value is applicable, if either the number of clock cycles T > (
f
SYS / 1.2) or
the prescaler value K2 > 17.
In all other cases for a timeframe of T
× TCS the accumulated jitter D
T is determined by:
DT [ns] = DTmax × [(1 - 0.058 × K2) × (T - 1) / (0.83 × fSYS - 1) + 0.058 × K2]
f
SYS in [MHz] in all formulas.
Example, for a period of 3 TCSs @ 33 MHz and K2 = 4:
Dmax = ±(220 / (4 × 33) + 4.3) = 5.97 ns (Not applicable directly in this case!)
D3 = 5.97 × [(1 - 0.058 × 4) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 4]
= 5.97
× [0.768 × 2 / 26.39 + 0.232]
= 1.7 ns
Example, for a period of 3 TCSs @ 33 MHz and K2 = 2:
Dmax = ±(220 / (2 × 33) + 4.3) = 7.63 ns (Not applicable directly in this case!)
D3 = 7.63 × [(1 - 0.058 × 2) × (3 - 1) / (0.83 × 33 - 1) + 0.058 × 2]
= 7.63
× [0.884 × 2 / 26.39 + 0.116]
= 1.4 ns
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