參數(shù)資料
型號(hào)： SAH-XC2712X-8F66R
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PDSO38
封裝： 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38
文件頁(yè)數(shù)： 22/103頁(yè)
文件大?。?/td> 2957K
代理商： SAH-XC2712X-8F66R
XC2712X
XC2000 Family / Compact Line
Functional Description
PRELIMINARY
Data Sheet
21
V1.0, 2010-12
3.1
Memory Subsystem and Organization
The memory space of the XC2712X is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XC2712X Memory Map 1)
Address Area
Start Loc. End Loc.
Area Size2)
Notes
IMB register space
FF’FF00H FF’FFFFH 256 bytes
Reserved
F0’0000H FF’FEFFH < 1 Mbyte
Minus IMB
registers.
Reserved for EPSRAM
E8’1000H EF’FFFFH 508 Kbytes
Mirrors EPSRAM
Emulated PSRAM
E8’0000H E8’0FFFH up to 4 Kbytes With Flash timing.
Reserved for PSRAM
E0’1000H E7’FFFFH 508 Kbytes
Mirrors PSRAM
PSRAM
E0’0000H E0’0FFFH up to 4 Kbytes Program SRAM.
Reserved for Flash
C1’1000H DF’FFFFH 1980 Kbytes
Flash 0
C0’0000H C1’0FFFH 68 Kbytes
3)
External memory area
40’0000H BF’FFFFH 8 Mbytes
External IO area4)
21’0000H 3F’FFFFH 1984 Kbytes
Reserved
20’B400H 20’FFFFH 19 Kbytes
USIC0 alternate regs.
20’B000H 20’B3FFH 1 Kbytes
Accessed via
LXBus controller
Reserved
20’4800H 20’AFFFH 26 Kbytes
USIC0 registers
20’4000H 20’47FFH 2 Kbytes
Accessed via
LXBus controller
Reserved
20’0000H 20’3FFFH 16 Kbytes
External memory area
01’0000H 1F’FFFFH 1984 Kbytes
SFR area
00’FE00H 00’FFFFH 0.5 Kbytes
Dual-port RAM
(DPRAM)
00’F600H 00’FDFFH 2 Kbytes
Reserved for DPRAM
00’F200H 00’F5FFH 1 Kbytes
ESFR area
00’F000H 00’F1FFH 0.5 Kbytes
XSFR area
00’E000H 00’EFFFH 4 Kbytes
Data SRAM (DSRAM)
00’D800H 00’DFFFH 2 Kbytes
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