參數(shù)資料
型號(hào)： SAH-XC2712X-8F66R
廠商： INFINEON TECHNOLOGIES AG
元件分類(lèi)： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PDSO38
封裝： 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38
文件頁(yè)數(shù)： 50/103頁(yè)
文件大?。?/td> 2957K
代理商： SAH-XC2712X-8F66R
XC2712X
XC2000 Family / Compact Line
Functional Description
PRELIMINARY
Data Sheet
46
V1.0, 2010-12
3.18
Instruction Set Summary
Table 11 lists the instructions of the XC2712X.
The addressing modes that can be used with a specific instruction, the function of the
instructions, parameters for conditional execution of instructions, and the opcodes for
each instruction can be found in the “Instruction Set Manual”.
This document also provides a detailed description of each instruction.
Table 11
Instruction Set Summary
Mnemonic
Description
Bytes
ADD(B)
Add word (byte) operands
2 / 4
ADDC(B)
Add word (byte) operands with Carry
2 / 4
SUB(B)
Subtract word (byte) operands
2 / 4
SUBC(B)
Subtract word (byte) operands with Carry
2 / 4
MUL(U)
(Un)Signed multiply direct GPR by direct GPR
(16-
× 16-bit)
2
DIV(U)
(Un)Signed divide register MDL by direct GPR (16-/16-bit) 2
DIVL(U)
(Un)Signed long divide reg. MD by direct GPR (32-/16-bit) 2
CPL(B)
Complement direct word (byte) GPR
2
NEG(B)
Negate direct word (byte) GPR
2
AND(B)
Bitwise AND, (word/byte operands)
2 / 4
OR(B)
Bitwise OR, (word/byte operands)
2 / 4
XOR(B)
Bitwise exclusive OR, (word/byte operands)
2 / 4
BCLR/BSET
Clear/Set direct bit
2
BMOV(N)
Move (negated) direct bit to direct bit
4
BAND/BOR/BXOR AND/OR/XOR direct bit with direct bit
4
BCMP
Compare direct bit to direct bit
4
BFLDH/BFLDL
Bitwise modify masked high/low byte of bit-addressable
direct word memory with immediate data
4
CMP(B)
Compare word (byte) operands
2 / 4
CMPD1/2
Compare word data to GPR and decrement GPR by 1/2
2 / 4
CMPI1/2
Compare word data to GPR and increment GPR by 1/2
2 / 4
PRIOR
Determine number of shift cycles to normalize direct
word GPR and store result in direct word GPR
2
SHL/SHR
Shift left/right direct word GPR
2
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