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參數(shù)資料
| 型號： | SAH-XC2712X-8F66R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PDSO38 |
| 封裝： | 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38 |
| 文件頁數(shù)： | 71/103頁 |
| 文件大?。?/td> | 2957K |
| 代理商： | SAH-XC2712X-8F66R |
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XC2712X
XC2000 Family / Compact Line
Summary of Features
PRELIMINARY
Data Sheet
3
V1.0, 2010-12
16/32-Bit Single-Chip Microcontroller
with 32-Bit Performance
XC2712X (XC2000 Family)
1
Summary of Features
For a quick overview and easy reference, the features of the XC2712X are summarized
here.
High-performance CPU with five-stage pipeline and MPU
– 15.2 ns instruction cycle @ 66 MHz CPU clock (single-cycle execution)
– One-cycle 32-bit addition and subtraction with 40-bit result
– One-cycle multiplication (16
× 16 bit)
– Background division (32 / 16 bit) in 21 cycles
– One-cycle multiply-and-accumulate (MAC) instructions
– Enhanced Boolean bit manipulation facilities
– Zero-cycle jump execution
– Additional instructions to support HLL and operating systems
– Register-based design with multiple variable register banks
– Fast context switching support with two additional local register banks
– 16 Mbytes total linear address space for code and data
– 1,024 Bytes on-chip special function register area (C166 Family compatible)
– Integrated Memory Protection Unit (MPU)
Interrupt system with 16 priority levels providing 46 interrupt nodes
– Selectable external inputs for interrupt generation and wake-up
– Fastest sample-rate 15.2 ns
Eight-channel interrupt-driven single-cycle data transfer with
Peripheral Event Controller (PEC), 24-bit pointers cover total address space
Clock generation from internal or external clock sources,
using on-chip PLL or prescaler
Hardware CRC-Checker with Programmable Polynomial to Supervise On-Chip
Memory Areas
On-chip memory modules
– 2 Kbytes on-chip dual-port RAM (DPRAM)
– 2 Kbytes on-chip data SRAM (DSRAM)
– 4 Kbytes on-chip program/data SRAM (PSRAM)
– Up to 64 Kbytes on-chip program memory (Flash memory)
– Memory content protection through Error Correction Code (ECC) for Flash
memory and through parity for RAMs
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