參數(shù)資料
型號(hào)： SAF82526N
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 79/126頁
文件大小： 730K
代理商： SAF82526N
Semiconductor Group
79
SAB 82525
SAB 82526
SAF 82525
SAF 82526
8
Detailed Register Description
8.1 Register Address Arrangement
Table 11
Layout of Register Addresses
A
B
Read
Write
Refer
to
page:
ADDRESS
Channel
REGISTER
73
74
00
:
:
1F
40
:
:
5F
RFIFO XFIFO Receive/Transmit FIFO
75
76
20
60
ISTA
MASK
Interrupt STAtus/Mask
79
80
21
61
STAR
CMDR STAtus/CoManD
82
22
62
MODE
MODE
84
23
63
TIMR
TIMer
85
85
24
64
EXIR
XAD1
EXtended Interrupt/Transmit ADdress 1
86
86
25
65
RBCL
XAD2
Receive Byte Count Low/Transmit ADdress 2
–
87
26
66
–
RAH1
Receive Address High 1
87
87
27
67
RSTA
RAH2
Receive STAtus/Rec. Addr. High 2
90
28
68
RAL1
Receive Address Low 1
91
90
29
69
RHCR
RAL2
Receive HDLC Control/Receive Addr. Low 2
–
92
2A
6A
–
XBCL
Transmit Byte Count Low
–
92
2B
6B
–
BGR
Baudrate Generator Register
93
2C
6C
CCR2
Channel Configuration Register 2
96
95
2D
6D
RBCH
XBCH
Receive/Transmit Byte Count High
96
97
2E
6E
VSTR
RLCR
Version STatus/Receive Frame Length Check
97
2F
6F
CCR1
Channel Configuration Register 1
–
99
30
70
–
TSAX
Time-Slot Assignment Transmit
–
99
31
71
–
TSAR
Time-Slot Assignment Receive
–
99
32
72
–
XCCR
Transmit Channel Capacity
–
99
33
73
–
RCCR
Receive Channel Capacity
Note:
Channel A is not implemented in SAB 82526
RAL1
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