參數(shù)資料
型號： SAF82526N
廠商： INFINEON TECHNOLOGIES AG
英文描述： Data Communications ICs
中文描述： 數(shù)據(jù)通信集成電路
文件頁數(shù)： 66/126頁
文件大?。?/td> 730K
代理商： SAF82526N
Semiconductor Group
66
SAF 82526
SAB 82525
SAB 82526
SAF 82525
6.3 Continuous Transmission (DMA Mode only)
If data transfer from system memory to the HSCX is done by DMA (DMA bit in XBCH set), the
number of bytes to be transmitted is usually defined via the Transmit Byte Count registers
(XBCH, XBCL : bits XBC11. . .XBC0).
Setting the "Transmit Continuously" (XC) bit in XBCH, however, the byte count value is ignored
and the DMA interface of the HSCX will continuously request for transmit data any time
32 bytes can be stored in the XFIFO.
This feature can be used e.g. to
continuously transmit voice or data onto a PCM highway (clock mode 5/extended
transparent mode), or to
transmit frames exceeding the byte count programmable via XBCH, XBCL (frames with
more than 4095 bytes).
Note:
If the XC bit is reset during continuous transmission, the transmit byte count becomes
valid again, and the HSCX will request the amount of DMA transfers programmed via
XBC11. . .XBC0. Otherwise the continuous transmission is stopped when a data
underrun condition occurs in the XFIFO, i.e. the DMA controller does not transfer further
data to the HSCX. In this case continuous ’1’-s (IDLE), without appending a CRC, are
transmitted.
1)
The frame length includes all bytes which are stored in the RFIFO.
6.4 Receive Length Check Feature
The HSCX offers the possibility to supervise the maximum length of received frames and to
terminate data reception in case this length is exceeded.
This feature is controlled via the special Receive Length Check Register (RLCR).
The function is enabled by setting the RC (Receive Check) bit in RLCR and programming the
maximum frame length via bits RL6. . .RL0
1)
.
According to the value written to RL6. . .RL0, the maximum receive length can be adjusted in
multiples of 32-byte blocks as follows:
MAX. LENGTH = (RL + 1)
×
32.
All frames exceeding this length are treated as if they have been aborted from the opposite
station, i.e. the CPU is informed via a
– RME interrupt, and the
– RAB bit in RSTA register is set!
To distinguish between frames really aborted from the opposite station, the receive byte count
(readable from RBCH, RBCL registers) exceeds the maximum receive length (via RL6. . .RL0)
by one or two bytes in this case.
The check includes all data that is copied into the RFIFO. It does not include the address byte
(s) if address recognition is selected. It includes the RSTA value in all operating modes.
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