參數資料
型號: SAF82526N
廠商: INFINEON TECHNOLOGIES AG
英文描述: Data Communications ICs
中文描述: 數據通信集成電路
文件頁數: 35/126頁
文件大小: 730K
代理商: SAF82526N
Semiconductor Group
35
SAB 82525
SAB 82526
SAF 82525
SAF 82526
Since the on-chip timer of the HSCX must be operated in the external mode (a secondary may
not poll the primary for acknowledgements), time supervisory must be done by the primary
station.
Upon the arrival of an acknowledgement the XFIFO is enabled and an interrupt is forwarded
to the CPU, either the
– message has been acknowledged as positive (XPR interrupt), or the
– message must be repeated (XMR interrupt).
Additionally, the timer can be used
under CPU control
to provide timer recovery of the
secondary if no acknowledgements are received at all.
Note:
The transmission of transparent frames is possible only if the permission to send is
achieved by an S-frame (p = 1) or
I
-frame.
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