參數(shù)資料
型號(hào): SAF7113
廠商: NXP Semiconductors N.V.
英文描述: 9-bit video input processor
中文描述: 9位視頻輸入處理器
文件頁(yè)數(shù): 74/80頁(yè)
文件大?。?/td> 281K
代理商: SAF7113
2000 May 08
74
Philips Semiconductors
Product specification
9-bit video input processor
SAF7113H
16 I
2
C-BUS START SET-UP
The given values force the following behaviour of the SAF7113H:
The analog input AI11 expects a signal in CVBS format; analog anti-alias filter and AGC active
Automatic field detection enabled, PAL BDGHI or NTSC M standard expected
Standard ITU 656 output format enabled, VBI-data slicer disabled; see Table 74 note 2
Contrast, brightness and saturation control in accordance with ITU standards
Chrominance processing with nominal bandwidth (800 kHz).
Table 74
I
2
C-bus start set-up values
SUB
(HEX)
FUNCTION
NAME
(1)
VALUES (BIN)
(HEX)
7
6
5
4
3
2
1
0
START
00
01
02
chip version
increment delay
analog input control 1
ID07 to ID04
X, X, X, X, IDEL3 to IDEL0
FUSE1 and FUSE0,GUDL1 and GUDL0,
MODE3 to MODE0
X, HLNRS, VBSL, WPOFF, HOLDG,
GAFIX, GAI28 and GAI18
GAI17 to GAI10
GAI27 to GAI20
HSB7 to HSB0
HSS7 to HSS0
AUFD, FSEL, FOET, HTC1, HTC0, HPLL,
VNOI1 and VNOI0
BYPS, PREF, BPSS1 and BPSS0, VBLB,
UPTCV, APER1 and APER0
BRIG7 to BRIG0
CONT7 to CONT0
read only
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
08
C0
03
analog input control 2
0
0
1
1
0
0
1
1
33
04
05
06
07
08
analog input control 3
analog input control 4
horizontal sync start
horizontal sync stop
sync control
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
00
00
E9
0D
98
09
luminance control
0
0
0
0
0
0
0
1
01
0A
0B
0C
0D
luminance brightness
luminance contrast
chrominance saturation SATN7 to SATN0
chrominance hue
control
chrominance control
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
80
47
40
00
HUEC7 to HUEC0
0E
CDTO, CSTD2 to CSTD0, DCCF, FCTC,
CHBW1 and CHBW0
ACGC, CGAIN6 to CGAIN0
0
0
0
0
0
0
0
1
01
0F
chrominance gain
control
format/delay control
0
0
1
0
1
0
1
0
2A
10
OFTS1 and OFTS0, HDEL1 and HDEL0,
VRLN, YDEL2 to YDEL0
GPSW1, CM99, GPSW0, HLSEL, OEYC,
OERT, VIPB and COLO
RTSE13 to RTSE10, RTSE03 to RTSE00
ADLSB, X, X, OLDSB, FIDP, X,
AOSL1 and AOSL0
0
0
0
0
0
0
0
0
00
11
output control 1
0
0
0
0
1
1
0
0
0C
12
13
output control 2
output control 3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
01
00
14
15
reserved
VGATE start
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00
00
VSTA7 to VSTA0
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