參數(shù)資料
型號(hào): SAF7113
廠商: NXP Semiconductors N.V.
英文描述: 9-bit video input processor
中文描述: 9位視頻輸入處理器
文件頁(yè)數(shù): 44/80頁(yè)
文件大?。?/td> 281K
代理商: SAF7113
2000 May 08
44
Philips Semiconductors
Product specification
9-bit video input processor
SAF7113H
Fig.30 Vertical timing diagram for 60 Hz [nominal input signal, VNL in normal mode (VNOI = 00), HPLL in VCR
or fast mode (HTC = 01 or 11)].
HREF: selectable on RTS0 and/or RTS1 via I
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = 7H.
ODD: selectable on RTS0 and/or RTS1 via I
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = AH.
VS: selectable on RTS0 and/or RTS1 via I
2
C-bus bits RTSE03 to 00 and/or RTSE13 to RTSE10 = BH.
V123: selectable on RTS0 and/or RTS1 via I
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = CH.
VREF: selectable on RTS0 and/or RTS1 via I
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = EH.
FID: selectable on RTS0 and/or RTS1 via I
2
C-bus bits RTSE03 to RTSE00 and/or RTSE13 to RTSE10 = FH.
(1) Line numbers in parenthesis refer to ITU line counting.
(2) VREF range short or long can be programmed via I
2
C-bus bit VRLN.
The luminance peaking and the chrominance trap are bypassed during VREF = 0 if I
2
C-bus bit VBLB is set to logic 1.
The chrominance delay line (chrominance-comb filter for NTSC, phase error correcting for PAL) is disabled during VREF = 0.
(3) FID changing line number and polarity programmable via VSTA8 to VSTA0 and FIDP, see Table 52.
(4) The inactive going edge of the V123-signal indicates whether the field is odd or even. If HREF is active during the falling edge of V123, the
field is
even
. If HREF is inactive during the falling edge of V123, the field is
odd
. The specific position of the slope is dependent on the internal
processing delay and may change a few clock cycles from version to version.
handbook, full pagewidth
RTS0/1 VS
VRLN = 1
(2)
(b) 2nd field
(a) 1st field
input CVBS
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(20)
(3)
(2)
(1)
(525)
(21)
(22)
(1)
VRLN = 1
(3) (2)
VRLN = 0
(3) (2)
1
2
3
4
5
6
7
8
17
525
524
523
522
18
19
(266)
(267)
(268)
(269)
(270)
(271)
(272)
(273)
(274)
(283)
(284)
(265)
(264)
(263)
(262)
263
264
265
266
267
268
269
270
271
280
281
262
261
260
259
(285)
(1)
282
MHB337
520
×
2/LLC
RTS0/1 ODD
81
×
2/LLC
VRLN = 0
(2)
RST0/1 HREF
RTS0/1 VREF
RTS0/1 VREF
RTS0/1 VREF
RTS0/1 VREF
RTS0/1 VS
RTS0/1 HREF
input CVBS
RTS0/1 ODD
RTS0/1 V123
(4)
RTS0/1 FID
(3)
RTS0/1 V123
(4)
RTS0/1 FID
(3)
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