參數(shù)資料
型號(hào): SAF7113
廠商: NXP Semiconductors N.V.
英文描述: 9-bit video input processor
中文描述: 9位視頻輸入處理器
文件頁(yè)數(shù): 48/80頁(yè)
文件大?。?/td> 281K
代理商: SAF7113
2000 May 08
48
Philips Semiconductors
Product specification
9-bit video input processor
SAF7113H
Table 22
Description of I
2
C-bus format; note 1
Notes
1.
2.
The SAF7113H supports the ‘fast mode’ I
2
C-bus specification extension (data rate up to 400 kbits/s).
If more than one byte DATA is transmitted the subaddress pointer is automatically incremented.
CODE
DESCRIPTION
S
Sr
Slave address W
START condition
repeated START condition
0100 1010 (= 4AH, default) or 0100 1000 (= 48H, if pin RTS0 strapped to ground via a 3.3 k
resistor)
0100 1011 (= 4BH, default) or 0100 1001 (= 49H, if pin RTS0 strapped to ground via a 3.3 k
resistor)
acknowledge generated by the slave
acknowledge generated by the master
subaddress byte; see Table 24
data byte; see Table 24; note 2
STOP condition
read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read
(the circuit is slave transmitter)
00H chip version
01H to 05H front-end part
06H to 13H decoder part
14H reserved
15H to 17H decoder part
18H to 1EH reserved
1FH video decoder status byte
20H to 3FH reserved
40H to 5EH general purpose data slicer
5FH reserved
60H to 62H general purpose data slicer status read only
63H to FFH reserved
Slave address R
ACK-s
ACK-m
Subaddress
Data
P
X = LSB slave
address
Subaddresses
read only
read and write
read and write
read and write
read only
read and write
ACK-s
ACK-m
SLAVE ADDRESS R
MHB340
P
Sr
ACK-s
ACK-s
DATA
SUBADDRESS
SLAVE ADDRESS W
S
data transferred
(n bytes + acknowledge)
Fig.34 Read procedure (combined format).
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