參數(shù)資料
型號: SAF7113
廠商: NXP Semiconductors N.V.
英文描述: 9-bit video input processor
中文描述: 9位視頻輸入處理器
文件頁數(shù): 24/80頁
文件大?。?/td> 281K
代理商: SAF7113
2000 May 08
24
Philips Semiconductors
Product specification
9-bit video input processor
SAF7113H
Table 2
Power-on control sequence
INTERNAL POWER-ON
CONTROL SEQUENCE
PIN OUTPUT STATUS
REMARKS
Directly after power-on
asynchronous reset
Synchronous reset
sequence
VPO7 to VPO0, RTCO, RTS0, RTS1,
SDA and LLC are in high-impedance state
LLC and SDA become active;
VPO7 to VPO0, RTCO, RTS0 and RTS1 are
held in high-impedance state
VPO7 to VPO0, RTCO, RTS0 and RTS1 are
held in high-impedance state
direct switching to high-impedance for
20 to 200 ms
internal reset sequence
Status after power-on
control sequence
after power-on (reset sequence) a complete
I
2
C-bus transmission is required
8.8
Multi-standard VBI data slicer
The multi-standard data slicer is a Vertical Blanking
Interval (VBI) and Full Field (FF) video data acquisition
block. In combination with software modules the slicer
acquires most existing formats of broadcast VBI and FF
data.
The implementation and programming model of the
multi-standard VBI data slicer is similar to the text slicer
built in the “Multimedia Video Data Acquisition Circuit
SAA5284”
The circuitry recovers the actual clock phase during the
clock-run-in-period, slices the data bits with the selected
data rate, and groups them into bytes. The clock
frequency, signals source, field frequency and accepted
error count must be defined via the I
2
C-bus in
subaddress 40H, AC1: bits D7 to D4.
Several standards can be selected per VBI line.
The supported VBI data standards are described in
Table 3.
The programming of the desired standards is done via
I
2
C-bus subaddresses 41H to 57H
(LCR2[7 : 0] to LCR24[7 : 0]); see detailed description in
Chapter 8.10. To adjust the slicers processing to the
signals source, there are offsets in horizontal and vertical
direction available via the I
2
C-bus in subaddresses 5BH
(bits 2 to 0), 59H (HOFF10 to HOFF0) and 5BH (bit 4),
5AH (VOFF8 to VOFF0). The formatting of the decoded
VBI data is done within the output interface to the
VPO-bus. For a detailed description of the sliced data
format see Table 17.
Table 3
Supported VBI standards
STANDARD TYPE
DATA RATE
(Mbits/s)
FRAMING CODE
FC
WINDOW
HAM
CHECK
Teletext EuroWST, CCST
European closed caption
VPS
Wide screen signalling bits
US teletext (WST)
US closed caption (line 21)
Teletext
VITC/EBU time codes (Europe)
VITC/SMPTE time codes (USA)
US NABTS
MOJI (Japanese)
Japanese format switch (L20/22)
6.9375
0.500
5
5
5.7272
0.503
6.9375
1.8125
1.7898
5.7272
5.7272
5
27H
001
9951H
1E3C1FH
27H
001
programmable
programmable
programmable
programmable
programmable (A7H)
programmable
WST625
CC625
VPS
WSS
WST525
CC525
general text
VITC625
VITC625
NABTS
Japtext
always
always
optional
optional
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