參數(shù)資料
型號: SAF7113
廠商: NXP Semiconductors N.V.
英文描述: 9-bit video input processor
中文描述: 9位視頻輸入處理器
文件頁數(shù): 52/80頁
文件大小: 281K
代理商: SAF7113
2000 May 08
52
Philips Semiconductors
Product specification
9-bit video input processor
SAF7113H
15.2
I
2
C-bus detail
The I
2
C-bus receiver slave address is 48H/49H.
Subaddresses 14H, 18H to 1EH, 20H to 3FH and
63H to FFH are reserved.
15.2.1
S
UBADDRESS
00H (
READ ONLY REGISTER
)
Table 25
Chip version SA 00
15.2.2
S
UBADDRESS
01H
Table 26
Horizontal increment delay
The programming of the horizontal increment delay is
used to match internal processing delays to the delay of
the ADC. Use recommended position only.
FUNCTION
LOGIC LEVELS
ID07
ID06
ID05
ID04
Chip Version (CV)
CV3
CV2
CV1
CV0
FUNCTION
IDEL3 IDEL2 IDEL1 IDEL0
No update
Minimum delay
Recommended
position
Maximum delay
1
1
1
1
1
0
1
1
0
1
0
0
0
0
0
0
15.2.3
S
UBADDRESS
02H
Table 27
Analog control 1 SA 02
Notes
1.
2.
Mode select (see Figs 35 to 42).
To take full advantage of the YC-modes 6 to 9 the I
2
C-bus bit BYPS (subaddress 09H, bit 7) should be set to logic 1
(full luminance bandwidth).
FUNCTION
(1)
CONTROL BITS D3 TO D0
MODE 3 MODE 2 MODE 1 MODE 0
Mode 0: CVBS (automatic gain) from AI11 (pin 4)
Mode 1: CVBS (automatic gain) from AI12 (pin 7)
Mode 2: CVBS (automatic gain) from AI21 (pin 43)
Mode 3: CVBS (automatic gain) from AI22 (pin 1)
Mode 4: reserved
Mode 5: reserved
Mode 6: Y (automatic gain) from AI11 (pin 4) + C (gain adjustable via
GAI28 to GAI20) from AI21 (pin 43); note 2
Mode 7: Y (automatic gain) from AI12 (pin 7) + C (gain adjustable via
GAI28 to GAI20) from AI22 (pin 1); note 2
Mode 8: Y (automatic gain) from AI11 (pin 4) + C (gain adapted to Y gain)
from AI21 (pin 43); note 2
Mode 9: Y (automatic gain) from AI12 (pin 7) + C (gain adapted to Y gain)
from AI22 (pin 1); note 2
Modes 10 to 15: reserved
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
1
1
1
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