參數(shù)資料
型號(hào)： SAF-XC2264N-16F40L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 68/131頁
文件大小： 1627K
代理商： SAF-XC2264N-16F40L
XC2261N/68N, XC2263N/64N/65N
XC2000 Family / Value Line
Functional Description
Data Sheet
41
V1.4, 2011-07
3.1
Memory Subsystem and Organization
The memory space of the XC226xN is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XC226xN Memory Map
1)
Address Area
Start Loc. End Loc.
Area Size
2)
Notes
IMB register space
FF’FF00
H
FF’FFFF
H
256 Bytes
Reserved
F0’0000
H
FF’FEFF
H
< 1 Mbyte
Minus IMB registers
Reserved for EPSRAM
E8’4000
H
EF’FFFF
H
496 Kbytes
Mirrors EPSRAM
Emulated PSRAM
E8’0000
H
E8’3FFF
H
up to
16 Kbytes
With Flash timing
Reserved for PSRAM
E0’4000
H
E7’FFFF
H
496 Kbytes
Mirrors PSRAM
PSRAM
E0’0000
H
E0’3FFF
H
up to
16 Kbytes
Program SRAM
Reserved for Flash
C5’0000
H
DF’FFFF
H
1,728 Kbytes
Flash 1
C4’0000
H
C4’FFFF
H
64 Kbytes
Flash 0
C0’0000
H
C3’FFFF
H
256 Kbytes
3)
Minus res. seg.
External memory area
40’0000
H
BF’FFFF
H
8 Mbytes
External IO area
4)
21’0000
H
3F’FFFF
H
1,984 Kbytes
Reserved
20’BC00
H
20’FFFF
H
17 Kbytes
USIC0–2 alternate regs. 20’B000
H
20’BBFF
H
3 Kbytes
Accessed via EBC
MultiCAN alternate regs. 20’8000
H
20’AFFF
H
12 Kbytes
Accessed via EBC
Reserved
20’5800
H
20’7FFF
H
10 Kbytes
USIC0–2 registers
20’4000
H
20’57FF
H
6 Kbytes
Accessed via EBC
Reserved
20’6800
H
20’7FFF
H
6 Kbytes
MultiCAN registers
20’0000
H
20’3FFF
H
16 Kbytes
Accessed via EBC
External memory area
01’0000
H
1F’FFFF
H
1984 Kbytes
SFR area
00’FE00
H
00’FFFF
H
0.5 Kbytes
Dualport RAM (DPRAM) 00’F600
H
00’FDFF
H
2 Kbytes
Reserved for DPRAM
00’F200
H
00’F5FF
H
1 Kbytes
ESFR area
00’F000
H
00’F1FF
H
0.5 Kbytes
XSFR area
00’E000
H
00’EFFF
H
4 Kbytes
Data SRAM (DSRAM)
00’A000
H
00’DFFF
H
16 Kbytes
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