參數(shù)資料
型號： SAF-XC2264N-16F40L
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100
封裝： 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù)： 26/131頁
文件大小： 1627K
代理商： SAF-XC2264N-16F40L
XC2261N/68N, XC2263N/64N/65N
XC2000 Family / Value Line
Electrical Parameters
Data Sheet
121
V1.4, 2011-07
4.7.7
Debug Interface Timing
The debugger can communicate with the XC226xN either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via DAP
The following parameters are applicable for communication through the DAP debug
interface.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 38 is valid under the following conditions:
C
L= 20 pF; voltage_range= upper
Table 39 is valid under the following conditions:
C
L= 20 pF; voltage_range= lower
Table 38
DAP Interface Timing for Upper Voltage Range
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
DAP0 clock period
1)
1) See the DAP chapter for clock rate restrictions in the Active::IDLE protocol state.
t
11 SR
25
ns
DAP0 high time
t
12 SR
8
ns
DAP0 low time
t
13 SR
8
ns
DAP0 clock rise time
t
14 SR
4ns
DAP0 clock fall time
t
15 SR
4ns
DAP1 setup to DAP0
rising edge
t
16 SR
6
ns
DAP1 hold after DAP0
rising edge
t
17 SR
6
ns
DAP1 valid per DAP0
clock period
2)
2) The Host has to find a suitable sampling point by analyzing the sync telegram response.
t
19 CC
17
20
ns
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