參數(shù)資料
型號(hào)： SAA7160ET
廠商： NXP Semiconductors N.V.
元件分類： PCI/cPCI/PXI
英文描述： PCI Express based audio and video bridge
封裝： SAA7160E/V2/R5<SOT879-1 (LBGA196)|<<http://www.nxp.com/packages/SOT879-1.html<1<Always Pb-free,;SAA7160ET/V2/R5<SOT951-1 (TFBGA88)|<<http://www.nxp.com/packages/SOT951-1.
文件頁(yè)數(shù)： 42/57頁(yè)
文件大小： 236K
代理商： SAA7160ET
SAA7160_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 25 February 2008
42 of 57
NXP Semiconductors
SAA7160
PCI Express based audio and video bridge
Any device addressed by a master is considered a slave. Generation of clock signals on
the I
2
C-bus is always the responsibility of the master device; each master generates its
own clock signals when transferring data on the bus. Bus clock signals from a master can
only be altered when they are stretched by a slow-slave device holding down the clock line
or by another master when arbitration occurs.
6.5 I
2
S-bus input interface
The SAA7160 has two independent audio slave interface circuits for serial input of digital
audio data streams. The audio interface circuits are based on the I
2
S-bus standard but
can be configured to several data and timing formats (with respect to framing, bit clock
and synchronization).
List of key features:
Supports
I
2
S-bus
, LSB and MSB justified formats
Sample size up to 32 bit
Standard stereo I
2
S-bus (MSB first, 1-bit delay from word select, left and right data in
a frame)
LSB first with 1-bit to 32-bits data per channel
Raw sample mode where the serial data for each active serial channel is sampled at
each sampling clock edge along with the word-select signal
Each of the slave I
2
S-bus interfaces consists two data lines, a word select line and a serial
clock line. The word select line distinguishes between the left and the right channel
information of the data lines. It is possible to sample up to 32 bits per channel, and there
are 4 channels on each module available.
The following block diagram shows the structure of the different I
2
S-bus interfaces.
Fig 10. I
2
C-bus structure overview
001aag990
CLOCK GENERATOR
I
2
C-BUS
CORE 1
IN
OUT
data I
2
C-bus control
I
2
C-bus configuration
IRQ
SDA_A
SCL_A
global I
2
C-bus
BOOT EEPROM
I
2
C-BUS
INTERFACE 2
CLOCK GENERATOR
I
2
C-BUS
CORE 0
IN
OUT
data I
2
C-bus control
I
2
C-bus configuration
IRQ
SDA_B
SCL_B
global I
2
C-bus
I
2
C-BUS
INTERFACE 1
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