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| 型號： | SAA7160ET |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | PCI/cPCI/PXI |
| 英文描述： | PCI Express based audio and video bridge |
| 封裝： | SAA7160E/V2/R5<SOT879-1 (LBGA196)|<<http://www.nxp.com/packages/SOT879-1.html<1<Always Pb-free,;SAA7160ET/V2/R5<SOT951-1 (TFBGA88)|<<http://www.nxp.com/packages/SOT951-1. |
| 文件頁數(shù)： | 36/57頁 |
| 文件大?。?/td> | 236K |
| 代理商： | SAA7160ET |
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SAA7160_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 25 February 2008
36 of 57
NXP Semiconductors
SAA7160
PCI Express based audio and video bridge
–
Overflow interrupt
Indicates that a buffer overflow has occurred in the corresponding DMA channel. It
should be noted that overflow interrupts are only generated for the AV DMA
channels (i.e. DMA channel 1 to 12).
Unmapped TC interrupt
The unmapped TC interrupt indicates the MMU dropped data packet with unmapped
TC.
AV interrupts
An AV interrupt indicates an interrupt event in the associated AV input (i.e. VIP, FGPI
or AI). An AV interrupt remains asserted HIGH until the interrupt status has been
cleared.
External interrupts from GPIO
External interrupts are assumed to be edge sensitive with programmable edge
polarity (i.e. rising and falling edge). Furthermore, external interrupts are assumed to
be asynchronous to the MSI clock domain and are synchronized internally before they
are actually being used. This imposes the constraint that an external interrupt must be
kept asserted for at least three MSI clock cycles to ensure proper synchronization.
In the event of simultaneous interrupts only one interrupt request can be served at the
same time.
6.3 Memory management unit
The MMUs’ main task is to translate the virtual, logical addresses of the DMA data packet
into the physical addresses that are used by the operating system. The virtual address
space is 32 bit, while the physical address space is 64 bit.
The main features of the MMU are:
Logical to physical address mapping
–
32-bit logical address
–
64-bit physical address: for legacy systems with 32-bit addressing, can be selected
for MMU physical address requirements
–
Support for 12 DMA channels
Support for multiple buffering
–
Managing address transfer for 8 buffer DMA handling
–
Maximum 8 memory buffers => 8 page table addresses per DMA channel =>
12
×
8 PTA
Support for buffer sizes larger than 2 MB
Support pre-fetching from page table to reduce latency
–
8 page table entries for 64-bit addressing
The virtual to physical address mapping is defined by the operating system using
so-called page tables. A page table is a 4 kB space in system memory. Each entry in a
page table contains the physical base address for 4 kB page of contiguous memory.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7160ET/V2 | 制造商:NXP Semiconductors 功能描述:SAA7160ET/TFBGA88/TRAYDPM//V2 - Trays |
| SAA7160ET/V2,557 | 制造商:Sigma Designs 功能描述:PCI Express based audio and video bridge 88-Pin TFBGA |
| SAA7162E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI Express based dual channel multistandard audio and video decoder |
| SAA7164 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| SAA7165 | 制造商:NXP Semiconductors 功能描述: |
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