參數(shù)資料
型號: SAA7160ET
廠商: NXP Semiconductors N.V.
元件分類: PCI/cPCI/PXI
英文描述: PCI Express based audio and video bridge
封裝: SAA7160E/V2/R5<SOT879-1 (LBGA196)|<<http://www.nxp.com/packages/SOT879-1.html<1<Always Pb-free,;SAA7160ET/V2/R5<SOT951-1 (TFBGA88)|<<http://www.nxp.com/packages/SOT951-1.
文件頁數(shù): 32/57頁
文件大?。?/td> 236K
代理商: SAA7160ET
SAA7160_1
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 — 25 February 2008
32 of 57
NXP Semiconductors
SAA7160
PCI Express based audio and video bridge
The input modules can be used in different combinations. The SAA7160E supports up to
a maximum of six simultaneous streams (e.g. six SD video streams, or four TS/PS
streams, or a combination of both). HD support is limited to one stream.
The SAA7160ET supports up to two simultaneous streams (e.g. two SD video streams,
two TS/PS streams, or a combination of both) and one HD stream.
In order to support all the possible use cases, six 10-bit wide input ports (port 1, port 2,
port 3, port 4, port 5, port 6) are required. The SAA7160E supports all six ports. The
SAA7160ET supports two ports only (port 2 and port 6).
Table 7
describes the combination of the video input modes.
The routing of the video input ports to the video input processors is implemented by a
multiplexer. The multiplexer is implemented such that each video input port drives VIP or
FGPI. The HD support is wired to two internal ports for VIP 0 and VIP 1 respectively.
The video input multiplexer takes care of routing the video input ports to the VIP and the
FGPI. The video input multiplexer includes one multiplexer for routing the VIP to the video
input processor and another one for routing the input ports to the FGPI.
Each 10-bit wide video input port can be used for capturing a single SD or TS/PS stream,
or two ports can be combined to capture an HD stream. Dependent on the stream type,
the port bits may serve a different purpose. Input streams can be either 8-bit or 10-bit
wide, and in case of 8-bit wide input streams the two LSBs of the video input port may be
used for the horizontal and vertical synchronization signals (href and vref).
Fig 6.
DVI system
10
001aag989
VIP
1
FGPI
3
port 1
PORT 1
DIGITAL VIDEO
INPUT INTERFACE
DIGITAL VIDEO INPUT
FGPI
2
DEVICE
TRANSACTION
LEVEL
PROTOCOL
10
port 2
PORT 2
DIGITAL VIDEO
INPUT INTERFACE
10
port 3
PORT 3
DIGITAL VIDEO
INPUT INTERFACE
10
VIP
0
FGPI
0
port 4
PORT 4
DIGITAL VIDEO
INPUT INTERFACE
FGPI
1
10
port 5
PORT 5
DIGITAL VIDEO
INPUT INTERFACE
10
port 6
PORT 6
DIGITAL VIDEO
INPUT INTERFACE
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