- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372114 > SAA7158 (NXP Semiconductors N.V.) Back END IC PDF資料下載
參數(shù)資料
| 型號(hào)： | SAA7158 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Back END IC |
| 中文描述： | 后端芯片 |
| 文件頁(yè)數(shù)： | 9/18頁(yè) |
| 文件大?。?/td> | 117K |
| 代理商： | SAA7158 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)
July 1994
9
Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
Data Path Signal processing
1H - 4:1:1 line memory, 852 words by 8-bits luminance
+
4-bits multiplexed chrominance
The Y/U/V line memory is organized as 852 x 12 bits. It
works as a shift register with recirculation mode if desired.
The line start is synchronized to RE, and if there are more
than 852 words to be stored it will stop and hold.
REFORMATTER to get 8-bit wide UV from the Y/U/V
bus format
The reformatter changes the 4:1:1 format of UV signals
into a sequential 8-bit U and V data stream with a sampling
rate of half the master clock.
MIX UV and MIX Y to interpolate between actual and
1H-delayed input signals, programmable for realization
of vertical zoom
The function of the MIX-blocks is to interpolate between
two input sources A and B (original signal and 1H-delayed
signal). Possible interpolation coefficients
1 or3
2
4
are
MEDIAN filter in luminance processing path for line
flicker reduction
The median filter consists of two different median filters
working in parallel with full clock rate. Filters for up and
downsampling are implemented with an 8-bit output.
MOVIE PHASE DETECT for supporting line flicker
reduction control
A pixel by pixel luminance level comparison is made on the
active video of two consecutive fields from the memory.
The absolute difference of the 4 most significant bits of
each pixel from the two fields is added to the accumulated
value of the current field in a register. The highest
significant two bytes thereof are transferred during field
blanking period with rising edge of RSTR signal into a
register that can be read via the
μ
P interface. After reading
the register will be cleared.
PEAKING for luminance channel
The H-peaking of the luminance channel compensates the
bandwidth reduction caused by various components of the
TV signal processing chain. Because of the possibility to
convert over and undershoots it is even possible to
precompensate the si-amplitude attenuation of the D/A
converter by 6 dB. The absolutely phaselinear filters can
be programmed: frequency response, amplitude of the
high frequency signals and degree of coring is controlled
via the
μ
P interface. Frequency responses c. f. separate
application sheet.
4 or1
---- or1
---- or 0
}
A
B
–
(
)
×
B.
+
{
UPSAMPLING and DCTI for chrominance transient
improvement
After upsampling of U and V, in the DCTI block the U and
V signals are processed with a
look-backwards/look-forwards device. The chrominance
signal values are stored in a 26 tap pixel delay line.
Controlled by a multiplexer select signal K the values are
read from the pixel delay line into the output registers of
DCTI. The calculation of the K signal is done within this
block. To determine the number of steps to look back and
forwards the following relation is used:
U and V are processed serially with the same circuitry. The
final upsampling towards the master clock for D/A
conversion is part of the algorithm and done by linear
interpolation between two adjacent taps of choice. It is
controlled by the K signal too.
HOLD/GREY/BLANK blocks for blanking and grey level
insertion
The function of these blocks is to insert desired levels for
Y, U and V, where no active video is present. BLANKing is
performed during line and field blanking period indicated
by BLN. GREY is performed where RE indicates that the
memory is not read out, and pixel repetition is switched off
by the
μ
P interface; the grey value comes via the
μ
P
interface. HOLD is performed if pixel repetition is selected
by the
μ
P interface; the last value of Y, U and V is kept until
RE is active again.
RE PROCESSING controls read enable for first and
second memory
Here the output signals RE1 and RE2 are shifted by
adding a programmable delay of 5, 6, 7 or 8 clock pulses
with respect to the input signals. In addition RE1 will be
influenced in case of zoom.
data switches for field select, mix/median select,
4:1:1/4:4:4 select
The switches shown in the block diagram Fig.3 are
controlled via the
μ
P interface and allow control of the data
streams inside the BENDIC.
DAC blocks for digital to analog conversion of Y, U, V
video signals
The D/A conversion is performed in the DAC blocks. The
converters consist of the resistor strings to be connected
externally and three buffers with a 25
serial resistor at
the output built in. To get 75
impedance externally three
50
resistors have to be used near the pins. The
capacitive load at the outputs should not exceed 30 pF.
d
dt
----
dt
dt
-------
˙˙
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA7158WP | Back END IC |
| SAA7165 | Digital Video Encoder EURO-DENC2 |
| SAA7183AWP | RECTIFIER SBR DUAL 30A 100V 200A-ifsm 850mV-vf 0.1mA-ir TO-220AB 50/TUBE |
| SAA7183A | Digital Video Encoder EURO-DENC2 |
| SAA7167 | YUV-to-RGB Digital-to-Analog Converter DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7158WP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Back END IC |
| SAA7160E | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI Express based audio and video bridge |
| SAA7160E/V1,557 | 制造商:NXP Semiconductors 功能描述: |
| SAA7160E/V2,557 | 制造商:NXP Semiconductors 功能描述: |
| SAA7160ET | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:PCI Express based audio and video bridge |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。