
July 1994
15
Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
Notes
1.
2.
f
CLK
= 36 MHz, f
data
= 18 MHz (rectangular full scale); without output load.
Timings and levels have to be measured with load circuits 1.2 k
connected to 3.0 V (TTL load), and C
L
= 25 pF.
APPLICATION NOTE FOR THE ANALOG PART OF BENDIC
The digital to analog conversion is done in parallel for the three channels. The DA converters (8-bit for U and V; 9-bit
for Y) are based on resistor strings with low impedance output buffers. They are designed for 2 V
p-p
unloaded output
swing. To avoid integral nonlinearity errors, the minimum output voltage is 200 mV; so the DC range for unloaded output
is between 0.2 and 2.2 V.
A serial resistor of 25
is integrated at the outputs of the buffers. With 50
in series - close to the output pins - the
nominal output voltage for 75
line termination is 1 V
p-p
with a DC range of 0.1 to 1.1 V. Amplitude matching to external
requirements has to be done with external dividers. Capacitance load should not exceed 30 pF.
The DAC’s require three separate analog supply voltages V
DDA1
3
and analog ground lines V
SSA1
3
for the output buffers.
The accuracy of an external voltage reference input V
DDA4
directly influences the output amplitude of the video signals.
The current input CUR supplies the output buffers with a current of about 0.3 mA at V
DDA
= 5 V, if a resistor of 15 k
is
connected to this pin.
A larger current improves the output bandwidth but makes the integral nonlinearity worse.
DNL
INL
V
out
differential nonlinearity
integral nonlinearity
output voltage (without load)
referred to 8 MSB’s
referred to 8 MSB’s
2 V
p-p
±
0.5
±
1
LSB
LSB
V
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT