參數(shù)資料
型號(hào): SAA7158
廠商: NXP Semiconductors N.V.
英文描述: Back END IC
中文描述: 后端芯片
文件頁(yè)數(shù): 4/18頁(yè)
文件大小: 117K
代理商: SAA7158
July 1994
4
Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
TEST1/AP
Y0-0
Y0-1
Y0-2
Y0-3
Y0-4
Y0-5
V
DD1
V
SS1
Y0-6
Y0-7
UV0-0
UV0-1
UV0-2
UV0-3
TEST2/SP
RE2_OUT
RE1_OUT
RSTR
RE2_IN
RE1_IN
BLN
μ
PCL
μ
PDA
V
SS2
CLK
V
DD2
V1-0/Y2-0
V1-1/Y2-1
V1-2/Y2-2
V1-3/Y2-3
V1-4/Y2-4
V1-5/Y2-5
V1-6/Y2-6
V1-7/Y2-7
U1-0/UV2-0
U1-1/UV2-1
U1-2/UV2-2
U1-3/UV2-3
V
SS3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
input
3-state output
3-state output
3-state output
3-state output
3-state output
3-state output
supply
ground
3-state output
3-state output
3-state output
3-state output
3-state output
3-state output
input
output
output
input
input
input
input
input
in/output
ground
input
supply
input
input
input
input
input
input
input
input
input
input
input
input
ground
action pin for testing; to be connected to V
SS
feedback_data to second memory, Y bit 0
feedback_data to second memory, Y bit 1
feedback_data to second memory, Y bit 2
feedback_data to second memory, Y bit 3
feedback_data to second memory, Y bit 4
feedback_data to second memory, Y bit 5
positive digital supply voltage (
+
5 V)
digital ground
feedback_data to second memory, Y bit 6
feedback_data to second memory, Y bit 7
feedback_data to second memory, UV bit 0
feedback_data to second memory, UV bit 1
feedback_data to second memory, UV bit 2
feedback_data to second memory, UV bit 3
shift pin for testing; to be connected to V
SS
redirected read enable to memory 2
redirected read enable to memory 1
memory read,
μ
P interface and movie detection reset
input for read enable to memory 2
input for read enable to memory 1
blanking signal
clock for interface with 8051 UART, mode 0
data for interface with 8051 UART, mode 0
digital ground
master clock, nominal 27 (32) MHz
positive digital supply voltage (
+
5 V)
V data, bit 0 in 4:4:4; Y data second memory, bit 0
V data, bit 1 in 4:4:4; Y data second memory, bit 1
V data, bit 2 in 4:4:4; Y data second memory, bit 2
V data, bit 3 in 4:4:4; Y data second memory, bit 3
V data, bit 4 in 4:4:4; Y data second memory, bit 4
V data, bit 5 in 4:4:4; Y data second memory, bit 5
V data, bit 6 in 4:4:4; Y data second memory, bit 6
V data, bit 7 in 4:4:4; Y data second memory, bit 7
U data, bit 0 in 4:4:4; UV data second memory, bit 0
U data, bit 1 in 4:4:4; UV data second memory, bit 1
U data, bit 2 in 4:4:4; UV data second memory, bit 2
U data, bit 3 in 4:4:4; UV data second memory, bit 3
digital ground
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