參數(shù)資料
型號(hào)： SAA7158
廠商： NXP Semiconductors N.V.
英文描述： Back END IC
中文描述： 后端芯片
文件頁(yè)數(shù)： 10/18頁(yè)
文件大?。?/td> 117K
代理商： SAA7158
July 1994
10
Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
REGISTER with 3-state control for direct output of Y/U/V
1 input to memories
The 3-state switch with internal register is supplied for the
feedback data to the second memory. The feedback bus is
a copy of the field 1 bus, but with 4 clockpulses delay.
3-state control is done via
μ
P interface.
The control signals
CLK
Line locked clock of maximal 36 MHz.
This is the system clock. Within the BENDIC the CLK
signal is distributed to the different blocks.
BLN
Blanking NOT signal.
This signal marks the horizontal and vertical blanking and
defines with its rising edge the start phase of the UV 4:1:1
format. A programmable delay of 0, 1, 2 or 3 clock pulses
shifts the internal pulse with respect to the input.
RE1_in
Read enable memory 1 signal.
This signal is generated by the memory controller and its
HIGH state determines the read enable on the first
memory bank, after it is processed by BENDIC for the
ZOOM mode and fine shift of the edges.
RE2_in
Read enable memory 2 signal.
This signal is generated by the memory controller and its
HIGH state determines the read enable on the second
memory bank, including a fine shift of the edges.
note:
RE1_in and RE2_in are processed in the BENDIC to:
external signals: RE1_out and RE2_out
RE with correct internal delay to match datapath delays,
is used to define the edges between video and side
panels (grey insertion or pixel repetition).
RSTR
Reset signal
This signal is transferred (asynchronous with CLK) by e. g.
a microprocessor to reset the communication between the
microprocessor and the BENDIC. CLK has to be present
in this case. In a typical application, RSTR is an active
HIGH pulse, issued only in the vertical blanking period.
During RSTR HIGH-state, the ‘feedback_data’ lines are
switched to 3-state, temporarily overruling the mode that
has been set by the microprocessor. By this provision,
RSTR can be used to prevent data collision on the 3-state
databus, e. g. during a power on sequence. Also, this
signal is used to transfer the ‘movie phase detect’ data to
a register that can be read by the microprocessor.
μ
PCL
Microprocessor interface clock signal
This signal is transferred (asynchronous with CLK) by a
microprocessor (8051, UART mode 0) as communication
clock signal at 1 MHz.
μ
PDA
Microprocessor interface data signal
This signal is transferred or received (asynchronous with
CLK) by a microprocessor (8051, UART mode 0) as
communication data signal at 1 MBaud, related to
μ
PCL.
Data is valid the rising edge of
μ
PCL.
The external control
The
μ
P interface has the following functions:
Receive settings from the
μ
P
Transmit movie phase detect data to the
μ
P
The interface is based on a two wire interface, one for
clock, the other for bidirectional data form. It is compatible
with the 8051 family UART mode 0 interface. The
μ
P is the
master of the communication, it generates the clock
(nominal 12 MHz/12 = 1 MHz), only active when transfer is
done.
The protocol for the communication is:
8 addressbits are sent by the
μ
P (LSB first), if the address
is a write address then 8 databits (LSB first) are sent by the
μ
P, else (if the address is a read address) 8 databits are
sent by BENDIC.
RSTR is used to reset the phase of the address/data
transfer. The negative going edge of RSTR clears the
address register. After reset the first transmitted bit is to be
taken as the first (LSB) bit of an address.
For field1/field2 selection and for mix/median selection, 4
addresses are used to select each of the four
combinations. A databyte is not obligatory after each of
these four addresses, but a dummy databyte is needed if
the transmission is to be followed by a further one.
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