參數(shù)資料
型號: SAA7158
廠商: NXP Semiconductors N.V.
英文描述: Back END IC
中文描述: 后端芯片
文件頁數(shù): 7/18頁
文件大?。?/td> 117K
代理商: SAA7158
July 1994
7
Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
FUNCTIONAL DESCRIPTION
Block Diagram
The BENDIC will be produced in a CMOS double metal process. It is possible to feed the BENDIC with 8-bit wide
luminance and chrominance signals Y/U/V in 4:1:1 mode from the digital Y/U/V bus and to run it in a bypass mode with
Y/U/V in 4:4:4 mode without any bandwidth reduction.
The BENDIC contains the processing functions as depicted in Fig.3.
Following functions are available:
Datapath:
1H - 4:1:1 line memory, 852 words by 8-bits luminance
+
4-bits multiplexed chrominance
REFORMATTER to get 8-bit wide UV from the Y/U/V bus format
MIX UV and MIX Y to interpolate between actual and 1H-delayed input signals, programmable for realization of vertical
zoom
MEDIAN filter in luminance processing path for line flicker reduction
MOVIE PHASE DETECT for supporting line flicker reduction control
PEAKING for luminance channel
UPSAMPLING and DCTI for chrominance transient improvement
HOLD/GREY/BLANK blocks for blanking and grey level insertion
RE PROCESSING controls read enable for first and second memory, outputs are programmable for different
applications
Data switches for field select, mix/median select, 4:1:1/4:4:4 select
DAC blocks for digital to analog conversion of Y, U, V video signals
REGISTER with 3-state control for direct output of Y/U/V 1 input to memories.
Control:
μ
P INTERFACE for the control of BENDIC functions, including zoom control
TIMING CONTROL and TEST as support blocks.
All video data signal processing inside the BENDIC is phaselinear and nonrecursive (except line delay in recirculation
mode).
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