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參數(shù)資料
| 型號(hào)： | SAA7138 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | The Digital Video Decoder/Encoder Modules(數(shù)字視頻譯碼器/編碼器模塊) |
| 中文描述： | 數(shù)字視頻解碼器/編碼器模塊（數(shù)字視頻譯碼器/編碼器模塊） |
| 文件頁數(shù)： | 28/53頁 |
| 文件大?。?/td> | 456K |
| 代理商： | SAA7138 |
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Module System: 7128MOD2
Philips Semiconductors
Application Note
AN 97085
Real Time Control
Enable
62H
If RTCE is set to high, Real Time Control (RTC) of the generated subcar-
rier frequency is enabled. RTC should be used whenever the clock for the
video encoder is generated by a digital line-locked video decoder to
ensure stable encoding phase for clean colors.
These registers directly influence the amplitude of the color burst for qua-
drature modulated standards (for SECAM, the amplitude of the color burst
cannot be modified!)
Usually, the nominal settings given in the datasheet should be used; in
case that an analog post filter contributes noticeable attenuation around
the subcarrier frequency, this parameter should be enlarged accordingly.
Burst Amplitude
62H
Subcarrier Fre-
quency
63H - 66H
The subcarrier frequency is synthesized by a 32 bit Discrete Time Oscilla-
tor; all four bytes are fully programmable
Closed Caption and Extended Data Service bytes to be downloaded inclu-
ding parity bit at the MSB position of each byte.
Handles input- or output signal of RCV1 and RCV2 pins (see correspon-
ding table in the datasheet).
Although the usual definition for master mode stands for trigger I/O’s to be
switched to output, the device allows for a kind of mixed mode as to be sla-
ved by a frame sync applied to pin RCV1 and simultaneously to output a
horizontal pulse on pin RCV2.
Sets the Horizontal Trigger phase related to signal on RCV1 or RCV2. If a
vertical sync is applied to RCV1, an additional horizontal sync at RCV2 is
needed to adjust the position of video horizontally.
Sets the Vertical Trigger phase related to the input signal on RCV1; value
VTRIG - counting half lines - should be even, only.
Interlaced operation or two different non-interlaced modes are selectable
for 525/60 signals or 625/50 signals.
depending on LDEL1 and LDL0 bits, an extra delay of the luminance
signal portion (for VBS or CVBS) can be added in order to compensate for
group delay distortions of the analog post filter.
Line 21 Encoding
67H - 6AH
RCV-Port Control
6BH
H-Trigger Control
6CH - 6DH
V- Trigger Control
6DH
Field Length Control
6EH
Luma Delay
6EH
Phase Reset Mode
of the colour subcar-
rier generator
6EH
These two bits should exactly be set acc. to the table in the datasheet. For
NTSC signals, both ’two-line reset’ or ’four-field reset’ are possible.
BLCKON
6EH
this bit set to low ensures normal operation, while set to high forces the all
signals to blanking level.
setting this bit to low will define the Vertical Blanking Interval by the values
loaded into registers FAL and LAL; if this bit is set to high, the Vertical
Blanking Intervall is forced acc. to CCIR-624 (50Hz) or acc. to RS170A
(60Hz)
Two bits enabling field-dependent insertion of Closed Caption/ Eyxtended
data.
For any line with Teletext insertion, this bit must be set to high, as it is a
master switch. The actual selection for activated Text lines is made below.
V-Blanking Definition 6EH
Individual Line 21
Encoding
6FH
Teletext Enable
6FH
Function
SubAdr
Description
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| SAA7140B | High Performance Scaler HPS |
| SAA7146AHZ | Circular Connector; No. of Contacts:66; Series:MS27472; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:18; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:18-35 RoHS Compliant: No |
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