參數(shù)資料
型號: SAA7138
廠商: NXP Semiconductors N.V.
英文描述: The Digital Video Decoder/Encoder Modules(數(shù)字視頻譯碼器/編碼器模塊)
中文描述: 數(shù)字視頻解碼器/編碼器模塊(數(shù)字視頻譯碼器/編碼器模塊)
文件頁數(shù): 14/53頁
文件大小: 456K
代理商: SAA7138
14
Module System: 7128MOD2
Philips Semiconductors
Application Note
AN 97085
2.6
Clock- and Synchronization signals
There are two operating modes for the encoder on this board. In master mode, V- and H- signals are output of
the RCV1 and RCV2 pins in order to synchronize an external source (e.g. memory or teletext).
In slave mode the synchronization signals H and V are generated out of the frame sync code embedded into the
CCIR-656 data stream or fed to the encoder via RCV1 and RCV2 (after passing JP23 and JP24). The configura-
tion of RCV1 and RCV2 (direction, polarity etc.) is handled in Reg. 6BH (Some information about register-
functions can be found on page 25). After a reset the RCV pins are programmed as inputs.
Regardless of master or slave mode operation, the system clock LLC can come from external or from the chip’s
own oscillator. Figures 4 and 5 show the respective jumper to configure clock direction. When an external clock is
received, JP27 and JP28 allow termination of LLC_1 and LLC_2 by adding a 240R resistor to ground. In addition
to this, series resistors (22R) terminate these clock lines.
Fig.4 Clock switching for SAA7138/39
Possible applications are:
- The internal oscillator provides the master clock by connecting XCLK and LLC1 (or LLC2). The buffered clock
signal at pin LLCOUT is switched to VG96 pin LLC for other circuits.
- An external oscillator can clock the device via VG96 pin CLK2_IN and JP13. Like in the first case, the buffe-
red clock signal at pin LLCOUT is switched to VG96 pin LLC for other circuits.
- An external oscillator can clock an external device (e.g. MPEG decoder). The clock signal comes in via
CLK2_IN and out via the buffered clock output LLCOUT and the VG96 pin CLKOUT.
a
b
c
SAA 7138/39
LLC2
XCLK
LLC1
LLCout
CLK2 IN (B20)
LLC (B17)
CLK OUT (B23)
JP13
JP13A
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