參數(shù)資料
型號(hào)： SAA4998H
廠商： NXP Semiconductors N.V.
英文描述： Field and line rate converter with noise reduction and embedded memory
中文描述： 場(chǎng)和符合降噪和嵌入式存儲(chǔ)器率轉(zhuǎn)換器
文件頁(yè)數(shù)： 8/39頁(yè)
文件大小： 175K
代理商： SAA4998H
2004 Feb 18
8
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SAA4998H
ACV/RE2
25
output/input
PIP mode disabled: active video output;
PIP mode enabled: read enable for PIP memory
PIP mode disabled: not connected;
PIP mode enabled: read reset for PIP memory
boundary scan test reset input (active LOW); with internal pull-up resistor
boundary scan test mode select input; with internal pull-up resistor
boundary scan test data input; with internal pull-up resistor
boundary scan test data output
boundary scan test clock input; with internal pull-up resistor
reset input; see Fig.4
SNERT bus reset input; with internal pull-down resistor
SNERT bus data input and output; with internal pull-down resistor
supply voltage of output pads (3.3 V)
PIP mode enable input
field memory ground
supply voltage of the internal field memories (1.8 V)
field memory ground
supply voltage of the internal field memories (1.8 V)
SNERT bus clock input; with internal pull-down resistor
bus A chrominance input bit 0 (LSB)
bus A chrominance input bit 1
bus A chrominance input bit 2
bus A chrominance input bit 3
bus A chrominance input bit 4
bus A chrominance input bit 5
core supply voltage (1.8 V)
core ground
to be connected to ground
supply voltage of the internal SRAMs (1.8 V)
ground of the internal SRAMs
bus A chrominance input bit 6
bus A chrominance input bit 7 (MSB)
bus A luminance input bit 0 (LSB)
bus A luminance input bit 1
bus A luminance input bit 2
bus A luminance input bit 3
bus A luminance input bit 4
bus A luminance input bit 5
bus A luminance input bit 6
bus A luminance input bit 7 (MSB)
read enable output for bus A
n.c./RSTR2
26
input
TRSTN
TMS
TDI
TDO
TCK
RST
SNRST
SNDA
V
DDE
PIPON
V
SSM
V
DDM
V
SSM
V
DDM
SNCL
UVA0
UVA1
UVA2
UVA3
UVA4
UVA5
V
DDD
V
SSD
TWOFMON
V
DDS
V
SSS
UVA6
UVA7
YA0
YA1
YA2
YA3
YA4
YA5
YA6
YA7
REA
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
input
input
input
3-state
input
input
input
input/output
supply
input
ground
supply
ground
supply
input
input
input
input
input
input
input
supply
ground
input
supply
ground
input
input
input
input
input
input
input
input
input
input
output
SYMBOL
PIN
TYPE
DESCRIPTION
(1)(2)(3)
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