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參數(shù)資料
| 型號： | SAA4998H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Field and line rate converter with noise reduction and embedded memory |
| 中文描述： | 場和符合降噪和嵌入式存儲器率轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/39頁 |
| 文件大?。?/td> | 175K |
| 代理商： | SAA4998H |
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2004 Feb 18
7
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SAA4998H
6
PINNING
SYMBOL
PIN
TYPE
DESCRIPTION
(1)(2)(3)
YG5/DPIP5
1
output/input
PIP mode disabled: bus G luminance output bit 5;
PIP mode enabled: PIP data input bit 5
PIP mode disabled: bus G luminance output bit 4;
PIP mode enabled: PIP data input bit 4
supply voltage of output pads (3.3 V)
ground of output pads
PIP mode disabled: bus G luminance output bit 3;
PIP mode enabled: PIP data input bit 3
PIP mode disabled: bus G luminance output bit 2;
PIP mode enabled: PIP data input bit 2
PIP mode disabled: bus G luminance output bit 1;
PIP mode enabled: PIP data input bit 1
PIP mode disabled: bus G luminance output bit 0 (LSB);
PIP mode enabled: PIP data input bit 0 (LSB)
PIP mode disabled: bus G chrominance output bit 7 (MSB);
PIP mode enabled: PIP data output bit 7 (MSB)
PIP mode disabled: bus G chrominance output bit 6;
PIP mode enabled: PIP data output bit 6
PIP mode disabled: bus G chrominance output bit 5;
PIP mode enabled: PIP data output bit 5
PIP mode disabled: bus G chrominance output bit 4;
PIP mode enabled: PIP data output bit 4
PIP mode disabled: bus G chrominance output bit 3;
PIP mode enabled: PIP data output bit 3
PIP mode disabled: not connected;
PIP mode enabled: line locked clock signal for PIP mode
ground of output pads
PIP mode disabled: not connected;
PIP mode enabled: serial write clock for PIP memory
PIP mode disabled: bus G chrominance output bit 2;
PIP mode enabled: PIP data output bit 2
PIP mode disabled: bus G chrominance output bit 1;
PIP mode enabled: PIP data output bit 1
PIP mode disabled: bus G chrominance output bit 0 (LSB);
PIP mode enabled: PIP data output bit 0 (LSB)
PIP mode disabled: not connected;
PIP mode enabled: write reset clock for PIP memory
PIP mode disabled: not connected;
PIP mode enabled: output enable for PIP memory output QPIPx
PIP mode disabled: not connected;
PIP mode enabled: input enable for PIP memory
high supply voltage of the internal field memories (3.3 V)
PIP mode disabled: not connected;
PIP mode enabled: write enable for PIP memory
YG4/DPIP4
2
output/input
V
DDE
V
SSE
YG3/DPIP3
3
4
5
supply
ground
output/input
YG2/DPIP2
6
output/input
YG1/DPIP1
7
output/input
YG0/DPIP0
8
output/input
UVG7/QPIP7
9
output
UVG6/QPIP6
10
output
UVG5/QPIP5
11
output
UVG4/QPIP4
12
output
UVG3/QPIP3
13
output
n.c./LLC
14
input
V
SSE
n.c./SWCK2
15
16
ground
input
UVG2/QPIP2
17
output
UVG1/QPIP1
18
output
UVG0/QPIP0
19
output
n.c./RSTW2
20
input
n.c./OIE2
21
input
n.c./IE2
22
input
V
DDP
n.c./WE2
23
24
supply
input
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