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| 型號： | SAA4998H |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Field and line rate converter with noise reduction and embedded memory |
| 中文描述： | 場和符合降噪和嵌入式存儲器率轉(zhuǎn)換器 |
| 文件頁數(shù)： | 30/39頁 |
| 文件大?。?/td> | 175K |
| 代理商： | SAA4998H |
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2004 Feb 18
30
Philips Semiconductors
Product specification
Field and line rate converter with noise
reduction and embedded memory
SAA4998H
10 CHARACTERISTICS
V
DDE
= 3.0 to 3.6 V; T
amb
= 0 to 70
°
C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
V
DDD
V
DDA
V
DDM
V
DDS
V
DDE
V
DDP
core supply voltage (internal rail)
analog supply voltage
field memory supply voltage
SRAM supply voltage
external supply voltage (output pads)
high supply voltage of internal field
memories
sum of supply current
at 1.8 V supply voltage pins
at 3.3 V supply voltage pins
1.65
1.8
1.95
V
3.0
3.3
3.6
V
I
DD
180
6
mA
mA
General
V
OH
V
OL
V
IH
V
IL
I
OH
HIGH-level output voltage
LOW-level output voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
V
DDE
0.4
2
4
0.4
0.8
V
V
V
V
mA
10 ns slew rate output;
V
OH
= V
DDE
0.4 V
10 ns slew rate output;
V
OL
= 0.4 V
I
OL
LOW-level output current
4
mA
C
i
I
LI
Outputs;
see Fig.5; note 2
input capacitance
input leakage current
8
1
pF
μ
A
note 1
I
OZ
t
d(o)
t
h(o)
Inputs
output current in 3-state mode
output delay time
output hold time
0.5 < V
o
< 3.6
4
1
23
μ
A
ns
ns
t
r
t
f
t
su(i)
t
h(i)
Input CLK32;
see Fig.5
rise time
fall time
input set-up time
input hold time
6
2
30
30
ns
ns
ns
ns
see Fig.5; note 3
see Fig.5; note 3
t
r
t
f
δ
T
cy
rise time
fall time
duty factor
cycle time
40
30
4
4
60
39
ns
ns
%
ns
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