參數(shù)資料
型號: SAA2502H
廠商: NXP SEMICONDUCTORS
元件分類: 消費家電
英文描述: ISO/MPEG Audio Source Decoder
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: PLASTIC, SOT-307, QFP-44
文件頁數(shù): 55/64頁
文件大?。?/td> 318K
代理商: SAA2502H
1997 Nov 17
55
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
Notes
1.
2.
T = 4
×
MCLKIN cycle time if MCLK24 = logic 1; T = 2
×
MCLKIN cycle time if MCLK24 = logic 0.
S is the audio sample time divided by 128.
a) Maximum external clock output load = 25 pF.
When CDCL is output (input master mode or buffer controlled mode).
When CDCL is input (input slave mode).
A negative value of t
PD
means that the output changes before the falling edge of the clock.
a) Propagation delay times are given with an external load of 0 pF.
b) Maximum external output load = 50 pF.
c) Output load derating of maximum propagation delay time is 0.5 ns per pF.
Sample frequency = 44.1 kHz.
3.
4.
5.
6.
Data inputs: CD, CDEF, CDSY, CDVAL, TDI and TMS
t
su
set-up time
CD, CDEF, CDSY and CDVAL
TDI and TMS
hold time CD, CDEF, CDSY and
CDVAL
set-up time CD, CDEF, CDSY and
CDVAL
hold time CD, CDEF, CDSY and
CDVAL
TDI and TMS HIGH time
CDCL clock; note 3
42
50
0
ns
ns
ns
t
h
CDCL clock; note 3
t
su
CDCL clock;
notes 1 and 4
CDCL clock; note 4
T + 10
ns
t
h
10
ns
t
H
50
ns
Data outputs
CDRQ
t
PD
SD
AND
WS
propagation delay time CDRQ
CDCL clock; note 5
22
+10
ns
t
PD
TDO
propagation delay time SD and WS SCK clock; note 5
22
+10
ns
t
PD
propagation delay time TDO
TCK clock; note 5
0
100
ns
Analog output performance;
note 6
THD + N
DR
α
cs
total harmonic distortion plus noise
dynamic range
channel separation
75
75
92
dB
dB
dB
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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