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參數(shù)資料
| 型號(hào)： | SAA2502H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ISO/MPEG Audio Source Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁數(shù)： | 18/64頁 |
| 文件大?。?/td> | 318K |
| 代理商： | SAA2502H |
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1997 Nov 17
18
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
7.4.3
S
AMPLE CLOCK GENERATION
When the ‘external sample clock’ mode of the clock
generator is used, the application must know the sample
rate. FSCLKIN has to be applied, with a frequency which
is a multiple of the sample rate. The (sample rate
dependent) output interface timing signals will be
generated from FSCLKIN. This mode will normally be
used in applications with a fixed sample rate. Should the
sample rate change, then a soft reset is strongly advised.
When one of the remaining clock generator modes is used,
the SAA2502 selects the active sample rate automatically,
and generates the required sample rate related timing
signals from its MCLKIN and X22IN clock inputs. Soft
resets at sample rate changes are generated
automatically. After a hard reset, a sample rate of 44.1 kHz
by default is selected. Such default setting may be
overruled using the control interface.
SCK, WS and SPDIF will show frequency changes in any
of the following 3 situations:
When the SAA2502 establishes synchronization to the
coded data input bit stream at a sample rate different
from the one previously selected
When the current (default) sample rate is overruled by
the control interface
When the clock generator mode is changed, resulting in
a switch from or to the ‘external sample clock mode.
In all those situation the phase of WS and the data content
of SPDIF will be continuous.
In all other events SCK, WS and SPDIF remain operating
without phase or frequency changes and the sample rate
selection remains unchanged.
7.4.4
D
ECODER PRECISION
During decoding several multiply operations are carried
out on coded samples. The results of these operations
have to be rounded in order to keep the word length
required for internal number representation within
reasonable limits. Accumulation of these rounding errors is
kept at a very low level in order to assure precise audio
output samples. SAA2502 precision is specified using the
output of the MPEG reference decoder based on double
precision floating point calculations as a reference.
Differences between that reference decoder and SAA2502
output manifest themselves as white noise.
Two contributions to this noise may be identified:
Noise resulting from internal rounding on intermediate
results
Noise resulting from rounding of final output samples
to 16, 18, 20 or 22 bits (depending on selected output
accuracy).
Table 8 shows the effective noise level figures. (unit is
1 LSB of 22-bit accuracy output). Except for 22-bit
accuracy, output rounding is by far the dominant effect.
Consequently the SAA2502 may be considered a
professional level high precision decoder.
Table 8
Effective noise level figures
Note
1.
The output rounding part of this precision is valid only for I
2
S and SPDIF outputs.
OUTPUT ACCURACY
(BITS)
INTERMEDIATE
ROUNDING
OUTPUT ROUNDING
(1)
TOTAL NOISE LEVEL
22
20
18
16
0.6
0.6
0.6
0.6
0.3
1.2
4.6
18.5
0.7
1.3
4.7
18.5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA2503 | MPEG2 audio decoder(MPEG2 音頻譯碼器) |
| SAA2503HT | MPEG2 audio decoder |
| SAA2505H-M1 | Digital multi-channel audio IC DUET |
| SAA2505 | Digital multi-channel audio IC DUET |
| SAA2505H | RES 4.99K OHM 1/16W 0.5% 0402SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA2503 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder |
| SAA2503HT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder |
| SAA2505 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
| SAA2505H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
| SAA2505H-M1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
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