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參數(shù)資料
| 型號(hào)： | SAA2502H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ISO/MPEG Audio Source Decoder |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, SOT-307, QFP-44 |
| 文件頁數(shù)： | 24/64頁 |
| 文件大小： | 318K |
| 代理商： | SAA2502H |
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1997 Nov 17
24
Philips Semiconductors
Preliminary specification
ISO/MPEG Audio Source Decoder
SAA2502
Table 13
Signals of output interfacing
The frequency of clock SCK is 64 times the sample
frequency.
The signal SD is the serial baseband audio data, sample
by sample (left/right interleaved; the left sample and the
right immediately following it form one stereo pair). 32 bits
are transferred per sample per channel. The samples are
transmitted in two’s complement, MSB first. The output
samples are rounded to either 16, 18, 20 or 22 bit
precision, selectable by the control interface flags RND1
and RND0. The remainder of the 32 transferred bits per
sample per channel are zero.
The word select signal WS indicates the channel of the
output samples (LOW if left, HIGH if right).
7.5.2
SPIDF
OUTPUT
7.5.2.1
SPIDF format
The SPDIF data format is frame based. One SPDIF frame
represents one audio sampling period. Complete frames
must be transmitted at the audio sample rate. Every frame
comprises two sub-frames, each of 32 bits. The data is
transmitted in bi-phase mark modulated format to ensure
a zero DC component.
Four bits of data at the beginning of each sub-frame are
assigned to frame and sub-frame synchronization, which
is achieved using a set of 3 output sequences which
violate the bi-phase mark rules. The audio samples
occupy 24 bits (bits 4 to 27), transmitted LSB first.
Depending on the selected accuracy the 2, 4, 6 or 8 LSBs
will be logic 0.
Bits 28 to 31 are occupied by the validity flag for the audio
sample, a channel status bit (each super-frame of
192 frames contains two groups of 192 channel status
bits, one for each channel), a user data bit, and a parity bit
(even parity for bits 4 to 31). These bits are described
respectively as V, U, C and P in the SPDIF specification.
The synchronization for the channel status frame is
achieved by a pair of preamble violation sequences.
The synchronization for the user channel data is
embedded within the data.
SIGNAL
DIRECTION
FUNCTION
SCK
SD
WS
output
output
output
data clock
baseband audio data
word select
7.5.2.2
Frame synchronization patterns (Bits 0 to 3,
SPDIF subframe)
The frame synchronization patterns are based on bi-phase
violations. They are sent as shown in Table 14
The sequences are sent in place of 4 bi-phase coded
bits 0 to 3. They are not bi-phase coded, but are sent as
they are.
Table 14
Frame synchronization patterns
7.5.2.3
Validity flag (bit 28, SPDIF subframe, V bit)
The V bit is intended to indicate an invalid data sample.
Equipment connected to the interface is expected to
perform interpolations across small numbers of invalid
(V = logic 1) samples. Owing to the manner in which data
is decoded in the SAA2502, and the sub-band processing
of the signal, an input data error affects output audio
signals in a complex way.
There is not a simple relationship between input errors and
damaged audio samples. Therefore the validity flag value
is made programmable (through the control interface unit)
Control software can use this bit in any way required.
7.5.2.4
User channel data (bit 29, SPDIF subframe,
U bit)
There is a single user data channel. Two bits of data in this
channel are transmitted in each frame. For this minimum
implementation only the possibility to send single byte user
messages to the user channel is offered. Each byte sent
will be preceded by a single logic 1 valued start bit.
The 8 bits of the user message are then sent LSB first.
7.5.2.5
Channel status data (bit 30, SPDIF sub-frame,
C bit)
A group of C channel status bits consists of 192 bits.
Two groups of channel status bits are transmitted every
super-frame (one group for each channel) at a rate of one
bit per sub-frame. In this application, both channel status
words will be identical.
BINARY
PATTERN
DESCRIPTION
11101000
B
left sub-frame follows.
SPDIF super-frame starts.
Bit 0 of left C channel will
be sent in this subframe
right subframe follows
left subframe follows
11100100
11100010
W
M
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SAA2503 | MPEG2 audio decoder(MPEG2 音頻譯碼器) |
| SAA2503HT | MPEG2 audio decoder |
| SAA2505H-M1 | Digital multi-channel audio IC DUET |
| SAA2505 | Digital multi-channel audio IC DUET |
| SAA2505H | RES 4.99K OHM 1/16W 0.5% 0402SMD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SAA2503 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder |
| SAA2503HT | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG2 audio decoder |
| SAA2505 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
| SAA2505H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
| SAA2505H-M1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital multi-channel audio IC DUET |
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