參數(shù)資料
型號: SAA2500
廠商: NXP Semiconductors N.V.
英文描述: MPEG Audio Source Decoder
中文描述: MPEG音頻源解碼器
文件頁數(shù): 30/47頁
文件大?。?/td> 199K
代理商: SAA2500
September 1994
30
Philips Semiconductors
Preliminary specification
MPEG Audio Source Decoder
SAA2500
S
PEED LIMITATIONS OF THE
L3
INTERFACE
When reading the status of, or writing control bytes to the
SAA2500, no status polling is necessary, so the speed of
these transfers is only limited by the maximum frequency
of signal L3CLK and the timing constraints of the L3
protocol.
When reading or writing data item bytes, status polling is
necessary. In addition to the speed limitation this poses,
the application must take precautions that individual data
item bytes are transferred at an interval of at least 200
μ
s.
Neither the status polling nor a minimum interval between
transfers is required when transferring the APU coefficient
item.
D
EFAULT ITEM DATA VALUES AFTER RESET
At a device reset, the L3 interface initialisation procedure
must be followed. All writeable data items are pre-loaded
with a defined default value after the device reset signal
has been de-activated. These default values are
summarised in Table 29.
Table 29
SAA2500 settings item; default value after device reset (notes 1 to 6.)
Notes
1.
MSEL1 = 0 and MSEL0 = 0; the master input is selected. The SAA2500 synchronizes to the ISO/MPEG
synchronization pattern.
CRCACT = 0; the SAA2500 uses the protection bit in the ISO/MPEG frame header to determine if the CRC is active.
MCKDIS = 0; the buffered master clock output MCLK is enabled.
2.
3.
4.
FCKENA = 0; the buffered 256f
s
or 384f
s
clock output is disabled.
SELCH2 = 0; when decoding input data with dual channel mode, channel I is output on both baseband audio output
channels.
RND1 = 0 and RND0 = 0; the baseband audio output signals are rounded to 16 bit.
5.
6.
Table 30
APU coefficients item; default values after device reset.
Notes
1.
2.
3.
4.
LL = 00000000; no attenuation in the left-to-left APU path.
LR = 01111111; infinite attenuation in the left-to-right APU path.
RL = 01111111; infinite attenuation in the right-to-left APU path.
RR = 00000000; no attenuation in the right-to-right APU path.
SUBSEQUENT
BYTES
7
6
5
4
3
2
1
0
SAA2500 settings
Value
MSEL1
0
MSEL0
0
CRCACT
0
MCKDIS
0
FCKENA
0
SELCH2
0
RND1
0
RND0
0
SUBSEQUENT
BYTES
APU coefficient LL
(1)
APU coefficient LR
(2)
APU coefficient RL
(3)
APU coefficient RR
(4)
7
6
5
4
3
2
1
0
0
0
0
0
LL.6 = 0
LR.6 = 1
RL.6 = 1
RR.6 = 0
LL.5 = 0
LR.5 = 1
RL.5 = 1
RR.5 = 0
LL.4 = 0
LR.4 = 1
RL.4 = 1
RR.4 = 0
LL.3 = 0
LR.3 = 1
RL.3 = 1
RR.3 = 0
LL.2 = 0
LR.2 = 1
RL.2 = 1
RR.2 = 0
LL.1 = 0
LR.1 = 1
RL.1 = 1
RR.1 = 0
LL.0 = 0
LR.0 = 1
RL.0 = 1
RR.0 = 0
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參數(shù)描述
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SAA2501H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Digital Audio Broadcast DAB decoder