
September 1994
27
Philips Semiconductors
Preliminary specification
MPEG Audio Source Decoder
SAA2500
SAA2500
SETTINGS ITEM
The SAA2500 is configured with the SAA2500 settings. The initial value of the SAA2500 settings after reset is all zeros.
Table 21
SAA2500 settings item; 1 byte (read/write).
Notes
1.
MSEL1 and MSEL0; these bits select the used input interface, the input data format and the input synchronization
type (see Table 22).
CRCACT; automatic/forced CRC activity:
a) CRCACT = 0; the SAA2500 uses the protection bit in the ISO/MPEG frame header to determine the presence of
the CRC.
b) CRCACT = 1; the SAA2500 assumes the CRC always to be present. The protection bit in the used ISO/MPEG
frame header is forced to 0.
MCKDIS; buffered master clock MCLK disabling:
a) MCKDIS = 0; enable MCLK.
b) MCKDIS = 1; disable (3-state) MCLK.
2.
3.
4.
FCKENA; buffered 256f
s
or 384f
s
output signal FSCLK enabling:
a) FCKENA = 0; disable (3-sate) FSCLK.
b) FCKENA = 1; enable FSCLK.
SELCH2; with dual channel mode input data (with other modes of input data ‘don’t care’:
a) SELCH2 = 0; select channel I.
b) SELCH2 = 1; select channel II.
RND1 and RND0; these bits select the rounding of the baseband audio output samples (see Table 23).
5.
6.
Table 22
MSEL1 and MSEL0.
Table 23
RND1 and RND0.
7
6
5
4
3
2
1
0
MSEL1
(1)
MSEL0
(1)
CRCACT
(2)
MCKDIS
(3)
FCKENA
(4)
SELCH2
(5)
RND1
(6)
RND0
(6)
MSEL1
MSEL0
USED INPUT INTERFACE
INPUT SYNCHRONIZATION
0
0
1
1
0
1
0
1
master
reserved
slave
slave
to ISO/MPEG synchronization pattern
reserved
to ISO/MPEG synchronization pattern
to synchronization signal CDSSY
RND1
RND0
OUTPUT SAMPLE ROUNDING LENGTH
0
0
1
1
0
1
0
1
16 bits
18 bits
20 bits
22 bits