參數(shù)資料
型號(hào)： SAA2023
廠商： NXP Semiconductors N.V.
英文描述： Drive processor for DCC systems
中文描述： 戴納信貸驅(qū)動(dòng)處理器的系統(tǒng)
文件頁(yè)數(shù)： 42/56頁(yè)
文件大小： 274K
代理商： SAA2023
May 1994
42
Philips Semiconductors
Preliminary specification
Drive processor for DCC systems
SAA2023
Table 45
Mapping of scratch pad RAM address for RAM quarter YZ = 00.
For The other three quarters of the RAM the mapping of the scratch pad RAM address onto the RACCNT and BYTCNT
registers is shown in Table 46.
Table 46
Mapping of scratch pad RAM address for RAM quarter YZ = 01, 10 and 11.
REGISTER
RACCNT
BYTCNT
BIT
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Value
P2
P1
P0
C2
C1
C0
1
1
R6
R5
R4
R3
R2
R1
R0
REGISTER
RACCNT
BYTCNT
BIT
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Value
P2
P1
P0
C2
C1
C0
R8
R7
R6
R5
R4
R3
R2
R1
R0
Mode changes
The possible mode changes for the TFE are shown in
Table 47.
Table 47
Mode changes.
T
IMING FOR
SAA2023
MODE CHANGES
Mode change DPAP to DRAR
This mode change occurs at the end of the time segment
in which the TFE module receives the new settings.
Writing of the first Main and AUX data to tape starts at the
start of the time segment 1 which occurs 2 ‘end of time
segment 3’ s after the mode change. The delay to writing
to tape is approximately 222 ms, as shown in Fig.35.
If ‘seamless appending’ is required the new settings
should be sent to the TFE module during time segment 2.
Mode change DPAP to DPAR
This mode change occurs at the first end of time
segment 2 after the TFE module receives the new
settings. Output of AUX to tape begins at the start of the
following time segment 1, (i.e. approximately85.3 ms after
the mode change), as shown in Fig.36.
CURRENT
MODE
NEW MODE
DPAP
yes
yes
DRAR
DPAR
DPAP
DRAR
DPAR
yes
no
yes
no
Mode change DRAR to DPAP
This mode change occurs at the first end of time
segment 0 after the TFE module receives the new setting.
Writing of Main and AUX data stops immediately after the
mode change.The time segment jumps back to logic 0,
URDA goes HIGH and stays HIGH for 5 time segments
(i.e. approximately 213.3 ms) after which it goes LOW, as
shown in Fig.37.
Mode change DPAR to DPAP
This mode change occurs at the first end of time
segment 0 after the TFE module receives the new setting.
The writing of AUX data to tape stops immediately after the
mode change. The first AUX read from tape can be
expected during the following time segment 0 or 1 (i.e.
approximately 128 to 170.67 ms after the mode change),
as shown in Fig.38.
Mode change DPAP to search
This mode change occurs almost instantaneously,
program the digital equalizer module in SAA2023 to go to
search mode, then program the interrupt mask register to
select the required type of interrupt.
Mode change search to DPAP
This mode change occurs almost instantaneously,
program the interrupt mask register to disable interrupts
program the digital equalizer module of SAA2023 to go to
normal mode. A re-synchronization will most likely occur
when as result of the data being read from tape, thus
causing URDA to go HIGH.
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